Travelled to:1 × France
2 × Germany
2 × USA
Collaborated with:D.Z.Pan A.Kumar T.Chen S.X.Shi G.Ganesan A.Rajaram P.Sithambaram K.Duraisami A.Macii E.Macii M.Poncino
Talks about:optim (3) clock (3) placement (2) framework (2) tree (2) skew (2) methodolog (1) nonlinear (1) structur (1) thermal (1)
Person: Ashutosh Chakraborty
DBLP: Chakraborty:Ashutosh
Contributed to:
2009
2009200820082006Wrote 5 papers:
- DAC-2009-ChakrabortyKP #framework #named #open source #quality
- RegPlace: a high quality open-source placement framework for structured ASICs (AC, AK, DZP), pp. 442–447.
- DATE-2009-ChakrabortyGRP #analysis #optimisation
- Analysis and optimization of NBTI induced clock skew in gated clock trees (AC, GG, AR, DZP), pp. 296–299.
- DAC-2008-ChenCP #framework
- An integrated nonlinear placement framework with congestion and porosity aware buffer planning (TCC, AC, DZP), pp. 702–707.
- DATE-2008-ChakrabortySP #layout #optimisation
- Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices (AC, SXS, DZP), pp. 849–855.
- DATE-2006-ChakrabortySDMMP #bound #optimisation
- Thermal resilient bounded-skew clock tree optimization methodology (AC, PS, KD, AM, EM, MP), pp. 832–837.