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Travelled to:
1 × France
2 × USA
Collaborated with:
Y.Shin I.Shin
Talks about:
high (3) synthesi (2) circuit (2) level (2) multiobject (1) standard (1) perform (1) element (1) zigzag (1) voltag (1)

Person: Seungwhun Paik

DBLP DBLP: Paik:Seungwhun

Contributed to:

DAC 20092009
DATE 20092009
DAC 20082008

Wrote 3 papers:

DAC-2009-ShinPS #synthesis #using
Register allocation for high-level synthesis using dual supply voltages (IS, SP, YS), pp. 937–942.
DATE-2009-PaikSS #named #performance #synthesis
HLS-l: High-level synthesis of high performance latch-based circuits (SP, IS, YS), pp. 1112–1117.
DAC-2008-PaikS #multi #optimisation #standard
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements (SP, YS), pp. 600–605.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.