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Travelled to:
2 × France
9 × USA
Collaborated with:
S.Paik I.Shin K.Choi J.Seomun T.Sakurai W.Chung S.Shim J.Kim D.Kim J.Kung I.Han S.S.Sapatnekar Y.Chuang S.Kim Y.Chang H.Kim H.Kim I.Eo
Talks about:
circuit (5) power (5) synthesi (3) system (3) design (3) optim (3) time (3) high (3) gate (3) cell (3)

Person: Youngsoo Shin

DBLP DBLP: Shin:Youngsoo

Contributed to:

DATE 20152015
DAC 20112011
DAC 20102010
DAC 20092009
DATE 20092009
DAC 20082008
DAC 20072007
DAC 20062006
DAC 20012001
DAC 20002000
DAC 19991999

Wrote 12 papers:

DATE-2015-ChungSS #identification
Identifying redundant inter-cell margins and its application to reducing routing congestion (WC, SS, YS), pp. 1659–1664.
DAC-2011-KungHSS #optimisation
Thermal signature: a simple yet accurate thermal index for floorplan optimization (JK, IH, SSS, YS), pp. 108–113.
DAC-2010-ChuangKSC #optimisation
Pulsed-latch aware placement for timing-integrity optimization (YLC, SK, YS, YWC), pp. 280–285.
DAC-2010-SeomunSS #implementation #power management #synthesis
Synthesis and implementation of active mode power gating circuits (JS, IS, YS), pp. 487–492.
DAC-2009-ShinPS #synthesis #using
Register allocation for high-level synthesis using dual supply voltages (IS, SP, YS), pp. 937–942.
DATE-2009-PaikSS #named #performance #synthesis
HLS-l: High-level synthesis of high performance latch-based circuits (SP, IS, YS), pp. 1112–1117.
DAC-2008-PaikS #multi #optimisation #standard
Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements (SP, YS), pp. 600–605.
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits (JS, JK, YS), pp. 103–106.
DAC-2006-KimSKE #design #physics #power management #standard
Physical design methodology of power gating circuits for standard-cell-based design (HOK, YS, HK, IE), pp. 109–112.
DAC-2001-ShinS #design #power management
Coupling-Driven Bus Design for Low-Power Application-Specific Systems (YS, TS), pp. 750–753.
DAC-2000-ShinKC #analysis #embedded #multi #performance #realtime
Schedulability-driven performance analysis of multiple mode embedded real-time systems (YS, DK, KC), pp. 495–500.
DAC-1999-ShinC #realtime #scheduling
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems (YS, KC), pp. 134–139.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.