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Travelled to:
1 × Germany
1 × United Kingdom
4 × USA
Collaborated with:
G.Wei D.M.Brooks S.Crespi-Reghizzi G.H.Holloway T.M.Jones V.J.Reddi M.Sykora G.Agosta N.Murphy T.M.J.0001 R.D.Mullins Enrico Armenio Deiana V.St-Amour P.A.Dinda N.Hardavellas Sotiris Apostolakis Ziyang Xu Greg Chan D.I.August M.S.Gupta M.D.Smith F.Sironi D.B.Bartolini F.Cancare H.Hoffmann D.Sciuto M.D.Santambrogio
Talks about:
parallel (5) automat (3) helix (3) softwar (2) program (2) perform (2) compil (2) level (2) loop (2) nondeterminist (1)

Person: Simone Campanoni

DBLP DBLP: Campanoni:Simone

Contributed to:

CGO 20152015
CGO 20122012
DAC 20122012
CC 20092009
DAC 20092009
DLT 20092009
CC 20162016
ASPLOS 20182018
ASPLOS 20202020

Wrote 10 papers:

CGO-2015-CampanoniHWB #named #parallel #semantics
HELIX-UP: relaxing program semantics to unleash parallelization (SC, GHH, GYW, DMB), pp. 235–245.
CGO-2012-CampanoniJHRWB #automation #named #parallel #source code
HELIX: automatic parallelization of irregular programs for chip multiprocessing (SC, TMJ, GHH, VJR, GYW, DMB), pp. 84–93.
DAC-2012-CampanoniJHWB #overview
The HELIX project: overview and directions (SC, TMJ, GHH, GYW, DMB), pp. 277–282.
DAC-2012-SironiBCCHSS #adaptation #named #operating system #performance #self
Metronome: operating system level performance management via self-adaptive computing (FS, DBB, SC, FC, HH, DS, MDS), pp. 856–865.
CC-2009-CampanoniSAC #compilation #jit #manycore
Dynamic Look Ahead Compilation: A Technique to Hide JIT Compilation Latencies in Multicore Environment (SC, MS, GA, SCR), pp. 220–235.
DAC-2009-ReddiGSWBC #challenge #hardware #reliability #stack
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack (VJR, SC, MSG, MDS, GYW, DMB), pp. 788–793.
DLT-2009-CampanoniC #control flow #graph
Traces of Control-Flow Graphs (SC, SCR), pp. 156–169.
CC-2016-MurphyJMC #automation #data flow #dependence #performance
Performance implications of transient loop-carried data dependences in automatically parallelized loops (NM, TMJ0, RDM, SC), pp. 23–33.
ASPLOS-2018-DeianaSDHC #nondeterminism #parallel
Unconventional Parallelization of Nondeterministic Applications (EAD, VSA, PAD, NH, SC), pp. 432–447.
ASPLOS-2020-ApostolakisXCCA #approach #automation #named #parallel
Perspective: A Sensible Approach to Speculative Automatic Parallelization (SA, ZX, GC, SC, DIA), pp. 351–367.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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