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Travelled to:
2 × France
9 × USA
Collaborated with:
D.M.Brooks M.S.Gupta G.H.Holloway S.Campanoni V.J.Reddi M.D.Smith S.L.Xi K.K.Rangan T.M.Jones M.D.Powell W.Kim Svilen Kanev H.M.Jacobson P.Bose J.L.Oatley R.Joseph X.Chen L.Peh Y.Huang P.R.Prucnal
Talks about:
voltag (3) helix (3) chip (3) use (3) processor (2) parallel (2) softwar (2) program (2) network (2) system (2)

Person: Gu-Yeon Wei

DBLP DBLP: Wei:Gu=Yeon

Contributed to:

CGO 20152015
HPCA 20152015
CGO 20122012
DAC 20122012
HPCA 20112011
DAC 20092009
DATE 20092009
HPCA 20092009
HPCA 20082008
DATE 20072007
HPCA 20052005
ASPLOS 20172017

Wrote 13 papers:

CGO-2015-CampanoniHWB #named #parallel #semantics
HELIX-UP: relaxing program semantics to unleash parallelization (SC, GHH, GYW, DMB), pp. 235–245.
HPCA-2015-XiJBWB #architecture #fault
Quantifying sources of error in McPAT and potential impacts on architectural studies (SLX, HMJ, PB, GYW, DMB), pp. 577–589.
CGO-2012-CampanoniJHRWB #automation #named #parallel #source code
HELIX: automatic parallelization of irregular programs for chip multiprocessing (SC, TMJ, GHH, VJR, GYW, DMB), pp. 84–93.
DAC-2012-CampanoniJHWB #overview
The HELIX project: overview and directions (SC, TMJ, GHH, GYW, DMB), pp. 277–282.
HPCA-2011-RanganPWB #performance #throughput
Achieving uniform performance and maximizing throughput in the presence of heterogeneity (KKR, MDP, GYW, DMB), pp. 3–14.
DAC-2009-ReddiGSWBC #challenge #hardware #reliability #stack
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack (VJR, SC, MSG, MDS, GYW, DMB), pp. 788–793.
DATE-2009-GuptaRHWB #approach
An event-guided approach to reducing voltage noise in processors (MSG, VJR, GHH, GYW, DMB), pp. 160–165.
HPCA-2009-ReddiGHWSB #predict #using
Voltage emergency prediction: Using signatures to reduce operating margins (VJR, MSG, GHH, GYW, MDS, DMB), pp. 18–29.
HPCA-2008-GuptaRSWB #commit #induction #named
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors (MSG, KKR, MDS, GYW, DMB), pp. 381–392.
HPCA-2008-KimGWB #analysis #performance #using
System level analysis of fast, per-core DVFS using on-chip switching regulators (WK, MSG, GYW, DMB), pp. 123–134.
DATE-2007-GuptaOJWB #comprehension #distributed #multi #network #using
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network (MSG, JLO, RJ, GYW, DMB), pp. 624–629.
HPCA-2005-ChenPWHP #design #power management
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems (XC, LSP, GYW, YKH, PRP), pp. 120–131.
ASPLOS-2017-KanevXWB #memory management #named
Mallacc: Accelerating Memory Allocation (SK, SLX, GYW, DMB), pp. 33–45.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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