BibSLEIGH — David_M

Travelled to:

1 × Mexico
17 × USA
2 × France

Collaborated with:

G.Wei B.C.Lee M.Martonosi M.S.Gupta G.H.Holloway V.J.Reddi S.Campanoni M.D.Smith R.Joseph S.L.Xi K.K.Rangan Y.Li Z.Hu K.Skadron T.M.Jones M.D.Powell W.Kim Svilen Kanev H.M.Jacobson P.Bose P.Bailis S.Gandhi M.I.Seltzer J.L.Oatley B.R.d.Supinski M.Schulz K.Singh S.A.McKee

Talks about:

perform (7) processor (5) microarchitectur (4) voltag (4) parallel (3) thermal (3) design (3) power (3) model (3) level (3)

Person: David M. Brooks

DBLP: Brooks:David_M=

Contributed to:

2015

2012

2011

2009

2008

2007

2006

2005

2003

2001

1999

2017

Wrote 23 papers:

CGO-2015-CampanoniHWB #named #parallel #semantics: HELIX-UP: relaxing program semantics to unleash parallelization (SC, GHH, GYW, DMB), pp. 235–245.
HPCA-2015-XiJBWB #architecture #fault: Quantifying sources of error in McPAT and potential impacts on architectural studies (SLX, HMJ, PB, GYW, DMB), pp. 577–589.
CGO-2012-CampanoniJHRWB #automation #named #parallel #source code: HELIX: automatic parallelization of irregular programs for chip multiprocessing (SC, TMJ, GHH, VJR, GYW, DMB), pp. 84–93.
DAC-2012-CampanoniJHWB #overview: The HELIX project: overview and directions (SC, TMJ, GHH, GYW, DMB), pp. 277–282.
DAC-2011-BailisRGBS #injection #named: Dimetrodon: processor-level preventive thermal management via idle cycle injection (PB, VJR, SG, DMB, MIS), pp. 89–94.
HPCA-2011-RanganPWB #performance #throughput: Achieving uniform performance and maximizing throughput in the presence of heterogeneity (KKR, MDP, GYW, DMB), pp. 3–14.
DAC-2009-ReddiGSWBC #challenge #hardware #reliability #stack: Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack (VJR, SC, MSG, MDS, GYW, DMB), pp. 788–793.
DATE-2009-GuptaRHWB #approach: An event-guided approach to reducing voltage noise in processors (MSG, VJR, GHH, GYW, DMB), pp. 160–165.
HPCA-2009-ReddiGHWSB #predict #using: Voltage emergency prediction: Using signatures to reduce operating margins (VJR, MSG, GHH, GYW, MDS, DMB), pp. 18–29.
ASPLOS-2008-LeeB #adaptation #architecture #performance #roadmap: Efficiency trends and limits from comprehensive microarchitectural adaptivity (BCL, DMB), pp. 36–47.
HPCA-2008-GuptaRSWB #commit #induction #named: DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors (MSG, KKR, MDS, GYW, DMB), pp. 381–392.
HPCA-2008-KimGWB #analysis #performance #using: System level analysis of fast, per-core DVFS using on-chip switching regulators (WK, MSG, GYW, DMB), pp. 123–134.
HPCA-2008-LeeB #architecture #design #optimisation: Roughness of microarchitectural design topologies and its implications for optimization (BCL, DMB), pp. 240–251.
DATE-2007-GuptaOJWB #comprehension #distributed #multi #network #using: Understanding voltage variations in chip multiprocessors using a distributed power-delivery network (MSG, JLO, RJ, GYW, DMB), pp. 624–629.
HPCA-2007-LeeB #architecture #design #modelling: Illustrative Design Space Studies with Microarchitectural Regression Models (BCL, DMB), pp. 340–351.
PPoPP-2007-LeeBSSSM #learning #modelling #parallel #performance: Methods of inference and learning for performance modeling of parallel applications (BCL, DMB, BRdS, MS, KS, SAM), pp. 249–258.
ASPLOS-2006-LeeB #architecture #modelling #performance #predict: Accurate and efficient regression modeling for microarchitectural performance and power prediction (BCL, DMB), pp. 185–194.
HPCA-2006-LiLBHS #constraints #design #physics: CMP design space exploration subject to physical constraints (YL, BCL, DMB, ZH, KS), pp. 17–28.
HPCA-2005-LiBHS #architecture #energy #performance #smt: Performance, Energy, and Thermal Considerations for SMT and CMP Architectures (YL, DMB, ZH, KS), pp. 71–82.
HPCA-2003-JosephBM #performance: Control Techniques to Eliminate Voltage Emergencies in High Performance Processors (RJ, DMB, MM), pp. 79–90.
HPCA-2001-BrooksM: Dynamic Thermal Management for High-Performance Microprocessors (DMB, MM), pp. 171–182.
HPCA-1999-BrooksM #performance: Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance (DMB, MM), pp. 13–22.
ASPLOS-2017-KanevXWB #memory management #named: Mallacc: Accelerating Memory Allocation (SK, SLX, GYW, DMB), pp. 33–45.