Travelled to:3 × USA
Collaborated with:S.Sahni E.Shragowitz C.Lo K.Chiang S.Yao C.Cheng D.Dutt
Talks about:effici (2) anneal (2) simul (2) time (2) combinatori (1) pitchmatch (1) extractor (1) algorithm (1) hierarch (1) compact (1)
Person: Surendra Nahar
DBLP: Nahar:Surendra
Contributed to:
1993198819861985Wrote 5 papers:
- DAC-1993-YaoCDNL #using
- Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP (SZY, CKC, DD, SN, CYL), pp. 395–400.
- DAC-1988-ChiangNL #algorithm #analysis #performance
- Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2 (KWC, SN, CYL), pp. 471–475.
- DAC-1986-NaharS #performance
- A time and space efficient net extractor (SN, SS), pp. 411–417.
- DAC-1986-NaharSS #combinator #optimisation
- Simulated annealing and combinatorial optimization (SN, SS, ES), pp. 293–299.
- DAC-1985-NaharSS
- Experiments with simulated annealing (SN, SS, ES), pp. 748–752.