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Travelled to:
1 × France
Collaborated with:
J.Koehl T.Ludwig B.Kick T.Pflueger
Talks about:
processor (1) perform (1) chipset (1) system (1) driven (1) design (1) time (1) high (1) flat (1) cmos (1)

Person: Ulrich Baur

DBLP DBLP: Baur:Ulrich

Contributed to:

DATE 19981998

Wrote 1 papers:

DATE-1998-KoehlBLKP #design
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset (JK, UB, TL, BK, TP), pp. 312–320.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.