Travelled to:1 × France
1 × Germany
2 × USA
Collaborated with:R.Tsay D.E.Lackey P.S.Zuchowski U.Baur T.Ludwig B.Kick T.Pflueger M.Bühler J.Bickford J.Hibbeler U.Schlichtmann R.Sommer M.Pronath A.Ripp
Talks about:design (4) perform (2) circuit (2) manufactur (1) technolog (1) processor (1) placement (1) influenc (1) approach (1) process (1)
Person: Jürgen Koehl
DBLP: Koehl:J=uuml=rgen
Contributed to:
2006
200319981991Wrote 4 papers:
- DATE-2006-BuhlerKBHSSPR #design #process
- DFM/DFY design for manufacturability and yield — influence of process variations in digital, analog and mixed-signal circuit design (MB, JK, JB, JH, US, RS, MP, AR), pp. 387–392.
- DAC-2003-LackeyZK #design
- Designing mega-ASICs in nanogate technologies (DEL, PSZ, JK), pp. 770–775.
- DATE-1998-KoehlBLKP #design
- A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset (JK, UB, TL, BK, TP), pp. 312–320.
- DAC-1991-TsayK #approach #optimisation #performance
- An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement (RST, JK), pp. 620–625.