BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
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Travelled to:
1 × France
1 × Germany
2 × USA
Collaborated with:
R.Tsay D.E.Lackey P.S.Zuchowski U.Baur T.Ludwig B.Kick T.Pflueger M.Bühler J.Bickford J.Hibbeler U.Schlichtmann R.Sommer M.Pronath A.Ripp
Talks about:
design (4) perform (2) circuit (2) manufactur (1) technolog (1) processor (1) placement (1) influenc (1) approach (1) process (1)

Person: Jürgen Koehl

DBLP DBLP: Koehl:J=uuml=rgen

Contributed to:

DATE 20062006
DAC 20032003
DATE 19981998
DAC 19911991

Wrote 4 papers:

DATE-2006-BuhlerKBHSSPR #design #process
DFM/DFY design for manufacturability and yield — influence of process variations in digital, analog and mixed-signal circuit design (MB, JK, JB, JH, US, RS, MP, AR), pp. 387–392.
DAC-2003-LackeyZK #design
Designing mega-ASICs in nanogate technologies (DEL, PSZ, JK), pp. 770–775.
DATE-1998-KoehlBLKP #design
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset (JK, UB, TL, BK, TP), pp. 312–320.
DAC-1991-TsayK #approach #optimisation #performance
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement (RST, JK), pp. 620–625.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.