Travelled to:1 × Canada
1 × China
1 × France
5 × USA
Collaborated with:B.Zang H.Chen J.Li C.Zhu Z.Fang Q.Min Q.Wang J.Chen M.Yang X.Qian Y.Wang Y.Li L.Liu C.Zhang H.Zhang Z.Wang R.Liu Y.Chen X.Wu C.Chen Y.Peng C.Chen W.Wu P.Yew T.Chen K.Zhou Y.Lu Y.Hu J.Li
Talks about:simul (3) optim (3) multicor (2) analysi (2) sampl (2) phase (2) multi (2) level (2) dynam (2) multithread (1)
Person: Weihua Zhang
DBLP: Zhang:Weihua
Contributed to:
2014
20132012
2012
2011
200920072006Wrote 8 papers:
- DAC-2014-ChenPCWMYZC #manycore #named #parallel #simulation #thread
- DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation (CCC, YCP, CFC, WSW, QM, PCY, WZ, TFC), p. 6.
- DATE-2013-LiZCZ #analysis #multi #simulation
- Multi-level phase analysis for sampling simulation (JL, WZ, HC, BZ), pp. 649–654.
- DAC-2012-FangMZLHZCLZ #manycore #named
- Transformer: a functional-driven cycle-accurate multicore simulator (ZF, QM, KZ, YL, YH, WZ, HC, JL, BZ), pp. 106–114.
- LCTES-2012-FangLZLCZ #analysis #multi #predict
- Improving dynamic prediction accuracy through multi-level phase analysis (ZF, JL, WZ, YL, HC, BZ), pp. 89–98.
- PPoPP-2011-WangLCWCZZ #named #parallel #scalability
- COREMU: a scalable and portable parallel full-system emulator (ZW, RL, YC, XW, HC, WZ, BZ), pp. 213–222.
- SAC-2009-ZhangLZZZZ #first-order #linear #optimisation
- Optimizing techniques for saturated arithmetic with first-order linear recurrence (WZ, LL, CZ, HZ, BZ, CZ), pp. 1883–1889.
- LCTES-2007-WangCZYZ #optimisation #performance
- Optimizing software cache performance of packet processing applications (QW, JC, WZ, MY, BZ), pp. 227–236.
- LCTES-2006-ZhangQWZZ #architecture #compilation #multi #optimisation
- Optimizing compiler for shared-memory multiple SIMD architecture (WZ, XQ, YW, BZ, CZ), pp. 199–208.