Travelled to:1 × Germany
7 × USA
Collaborated with:S.Chou C.Wen ∅ J.Baer C.Chen K.Chang J.Shen H.Tsai K.Yang Y.Peng M.Chang T.Lin A.P.Su J.Chu W.Ku J.Guo C.Lin Y.Tsao Y.Chan C.Wang J.Wang C.Chen W.Wu Q.Min P.Yew W.Zhang T.Yang L.Huang C.Chuang
Talks about:non (6) cach (3) multithread (2) volatil (2) program (2) switch (2) memori (2) intrus (2) energi (2) design (2)
Person: Tien-Fu Chen
DBLP: Chen:Tien=Fu
Contributed to:
20152014
2010200920072006
1998
1992Wrote 10 papers:
- DAC-2015-TsaiYPLTCC #design #energy #in memory #memory management #using
- Energy-efficient non-volatile TCAM search engine design using priority-decision in memory technology for DPI (HJT, KHY, YCP, CCL, YHT, MFC, TFC), p. 6.
- DAC-2014-ChenPCWMYZC #manycore #named #parallel #simulation #thread
- DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation (CCC, YCP, CFC, WSW, QM, PCY, WZ, TFC), p. 6.
- DAC-2014-TsaiCYYHCCC #energy #using
- Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination (HJT, CCC, KHY, TCY, LYH, CHC, MFC, TFC), p. 6.
- DATE-2010-WenCCL #debugging #named #parallel #runtime #source code
- RunAssert: A non-intrusive run-time assertion for parallel programs debugging (CNW, SHC, TFC, TJL), pp. 287–290.
- DAC-2009-ChouCWCCWW #3d #manycore
- No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips (SHC, CCC, CNW, YCC, TFC, CCW, JSW), pp. 587–592.
- DAC-2009-WenCCS #architecture #concurrent #debugging #detection #manycore #named
- NUDA: a non-uniform debugging architecture and non-intrusive race detection for many-core (CNW, SHC, TFC, APS), pp. 148–153.
- DAC-2007-ChuKCCG #embedded #multi #programming #thread
- An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model (JCC, WCK, SHC, TFC, JIG), pp. 652–657.
- DAC-2006-ChangSC #design #evaluation #trade-off
- Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs (KCC, JSS, TFC), pp. 143–148.
- HPCA-1998-Chen #adaptation #branch #execution
- Supporting Highly-Speculative Execution via Adaptive Branch Trees (TFC), pp. 185–194.
- ASPLOS-1992-ChenB #latency #memory management
- Reducing Memory Latency via Non-blocking and Prefetching Caches (TFC, JLB), pp. 51–61.