Travelled to:2 × USA
Collaborated with:T.Chen S.Chou C.Wen Y.Chan C.Wang J.Wang Y.Peng C.Chen W.Wu Q.Min P.Yew W.Zhang H.Tsai K.Yang T.Yang L.Huang C.Chuang M.Chang
Talks about:cach (2) interconnect (1) multithread (1) multicor (1) volatil (1) partial (1) lifetim (1) leverag (1) redund (1) energi (1)
Person: Chien-Chih Chen
DBLP: Chen:Chien=Chih
Contributed to:
20142009Wrote 3 papers:
- DAC-2014-ChenPCWMYZC #manycore #named #parallel #simulation #thread
- DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation (CCC, YCP, CFC, WSW, QM, PCY, WZ, TFC), p. 6.
- DAC-2014-TsaiCYYHCCC #energy #using
- Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination (HJT, CCC, KHY, TCY, LYH, CHC, MFC, TFC), p. 6.
- DAC-2009-ChouCWCCWW #3d #manycore
- No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips (SHC, CCC, CNW, YCC, TFC, CCW, JSW), pp. 587–592.