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Travelled to:
2 × France
3 × Germany
Collaborated with:
K.A.Hoque O.A.Mohamed A.Chureau E.M.Aboulhamid A.Abderrahman B.Kaminska N.Ignat B.Nicolescu G.Nicolescu B.Antaki N.Xiong S.Adham
Talks about:
system (3) circuit (2) analysi (2) model (2) probabilist (1) transactor (1) simultan (1) satellit (1) prototyp (1) maintain (1)

Person: Yvon Savaria

DBLP DBLP: Savaria:Yvon

Contributed to:

DATE 20152015
DATE 20062006
DATE 20052005
DATE 19991999
EDAC-ETC-EUROASIC 19941994

Wrote 5 papers:

DATE-2015-HoqueMS #analysis #approach #maintenance #model checking #probability #reliability #towards
Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking (KAH, OAM, YS), pp. 1635–1640.
DATE-2006-IgnatNSN #classification #impact analysis #operating system #realtime
Soft-error classification and impact analysis on real-time operating systems (NI, BN, YS, GN), pp. 182–187.
DATE-2005-ChureauSA #functional #prototype #uml
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application (AC, YS, EMA), pp. 698–703.
DATE-1999-AntakiSXA #design #testing
Design For Testability Method for CML Digital Circuits (BA, YS, NX, SA), pp. 360–367.
EDAC-1994-AbderrahmanKS #estimation
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits (AA, BK, YS), p. 658.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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