Travelled to:1 × Germany
Collaborated with:Y.Yang J.Anderson A.G.Veneris B.Le Alberto Delmas Lascorz Patrick Judd Dylan Malone Stuart Mostafa Mahmoud Sayeh Sharify M.Nikolic Kevin Siu A.Moshovos
Talks about:bit (2) reconfigur (1) sparsiti (1) function (1) approach (1) softwar (1) product (1) network (1) leverag (1) hardwar (1)
Person: Zissis Poulos
DBLP: Poulos:Zissis
Contributed to:
2012
2019Wrote 2 papers:
- DATE-2012-PoulosYAVL #debugging #functional
- Leveraging reconfigurability to raise productivity in FPGA functional debug (ZP, YSY, JA, AGV, BL), pp. 292–295.
- ASPLOS-2019-LascorzJSPMSNSM #approach #hardware #named #network
- Bit-Tactical: A Software/Hardware Approach to Exploiting Value and Bit Sparsity in Neural Networks (ADL, PJ, DMS, ZP, MM, SS, MN, KS, AM), pp. 749–763.