BibSLEIGH — Andreas_G

Travelled to:

3 × USA
4 × Germany
6 × France

Collaborated with:

S.Safarpour B.Keng Y.Yang B.Le H.Mangassarian R.Berryhill R.Drechsler M.S.Abadir N.Nicolici G.Baeckler R.Yuan G.Fey P.J.Thadikaran S.Venkataraman J.Lee J.B.Liu M.Amiri Z.Poulos J.Anderson A.Goultiaeva F.Bacchus S.Sinha R.K.Brayton D.E.Smith F.N.Najm

Talks about:

debug (7) autom (5) base (5) sat (4) boolean (3) design (3) function (2) diagnosi (2) abstract (2) satisfi (2)

Person: Andreas G. Veneris

DBLP: Veneris:Andreas_G=

Contributed to:

2015

2012

2011

2010

2009

2007

2006

2005

2004

2002

Wrote 16 papers:

DATE-2015-BerryhillV #automation #functional: Automated rectification methodologies to functional state-space unreachability (RB, AGV), pp. 1401–1406.
DAC-2012-KengV #abstraction #debugging #design #refinement #satisfiability: Path directed abstraction and refinement in SAT-based design debugging (BK, AGV), pp. 947–954.
DATE-2012-LeMKV #debugging #satisfiability #using: Non-solution implications using reverse domination in a modern SAT-based debugging environment (BL, HM, BK, AGV), pp. 629–634.
DATE-2012-PoulosYAVL #debugging #functional: Leveraging reconfigurability to raise productivity in FPGA functional debug (ZP, YSY, JA, AGV, BL), pp. 292–295.
DATE-2011-KengSV #automation #debugging: Automated debugging of SystemVerilog assertions (BK, SS, AGV), pp. 323–328.
DATE-2010-MangassarianLGVB #preprocessor: Leveraging dominators for preprocessing QBF (HM, BL, AG, AGV, FB), pp. 1695–1700.
DAC-2009-VenerisS: The day Sherlock Holmes decided to do EDA (AGV, SS), pp. 631–634.
DATE-2009-YangNV #automation #data analysis #debugging: Automated data analysis solutions to silicon debug (YSY, NN, AGV), pp. 982–987.
DATE-2009-YangSVBS #approximate #logic: Sequential logic rectifications with approximate SPFDs (YSY, SS, AGV, RKB, DES), pp. 1698–1703.
DATE-2007-MangassarianVSNA #estimation #process #pseudo #satisfiability #using: Maximum circuit activity estimation using pseudo-boolean satisfiability (HM, AGV, SS, FNN, MSA), pp. 1538–1543.
DATE-2007-SafarpourV #abstraction #automation #debugging #design #refinement: Abstraction and refinement techniques in automated design debugging (SS, AGV), pp. 1182–1187.
DAC-2006-SafarpourVBY #performance #satisfiability: Efficient SAT-based Boolean matching for FPGA technology mapping (SS, AGV, GB, RY), pp. 466–471.
DATE-2006-FeySVD #on the #satisfiability: On the relation between simulation-based and SAT-based diagnosis (GF, SS, AGV, RD), pp. 1139–1144.
DATE-2005-YangVTV #automation #debugging #design #fault #modelling #power management: Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs (YSY, AGV, PJT, SV), pp. 996–1001.
DATE-v1-2004-SafarpourVDL #satisfiability: Managing Don’t Cares in Boolean Satisfiability (SS, AGV, RD, JL), pp. 260–265.
DATE-2002-VenerisLAA #fault #incremental #multi: Incremental Diagnosis and Correction of Multiple Faults and Errors (AGV, JBL, MA, MSA), pp. 716–721.