19 papers:
DAC-2015-ShafiqueAHH #configuration management #latency- A low latency generic accuracy configurable adder (MS, WA, RH, JH), p. 6.
DATE-2015-HuQ #approximate #fault- A new approximate adder with low relative error and correct sign calculation (JH, WQ), pp. 1449–1454.
- DATE-2014-PerriconeHNN #3d #case study #design #logic
- Design of 3D nanomagnetic logic circuits: A full-adder case study (RP, XSH, JN, MTN), pp. 1–6.
- DAC-2013-RoyCPP #parallel #synthesis #towards #trade-off
- Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures (SR, MRC, RP, DZP), p. 8.
- DAC-2012-KahngK #approximate #configuration management #design
- Accuracy-configurable adder for approximate arithmetic designs (ABK, SK), pp. 820–825.
- DATE-2012-KotiyalTR #design
- Mach-Zehnder interferometer based design of all optical reversible binary adder (SK, HT, NR), pp. 721–726.
- DATE-2011-BruschiPRS #automaton #performance
- An efficient Quantum-Dot Cellular Automata adder (FB, FP, VR, DS), pp. 1220–1223.
- DATE-2011-ThapliyalR #design
- A new reversible design of BCD adder (HT, NR), pp. 1180–1183.
- DATE-2010-LauLCB #probability
- A general mathematical model of probabilistic ripple-carry adders (MSKL, KVL, YCC, AB), pp. 1100–1105.
- DATE-2008-GhoshNR #adaptation #fault tolerance #novel #using
- A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking (SG, PN, KR), pp. 366–371.
- DATE-2008-RaoO #fault tolerance #parallel #towards
- Towards fault tolerant parallel prefix adders in nanoelectronic systems (WR, AO), pp. 360–365.
- DATE-v2-2004-SogomonyanMOG #self
- A New Self-Checking Sum-Bit Duplicated Carry-Select Adder (ESS, DM, VO, MG), pp. 1360–1361.
- DATE-v2-2004-ZieglerS #design #parallel
- A Unified Design Space for Regular Parallel Prefix Adders (MMZ, MRS), pp. 1386–1387.
HPCA-2002-BrownP #pipes and filters #using- Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files (MDB, YNP), pp. 289–298.
- DAC-2001-YuYW #representation #synthesis #using
- Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits (ZY, MLY, ANWJ), pp. 456–461.
- DATE-2001-DrozdL #float #online #performance #testing
- Efficient on-line testing method for a floating-point adder (AVD, MVL), pp. 307–313.
- DAC-1998-KimJT #optimisation #using
- Arithmetic Optimization Using Carry-Save-Adders (TK, WJ, SWKT), pp. 433–438.
CAV-1998-ChenB #float #verification- Verification of Floating-Point Adders (YAC, REB), pp. 488–499.
- DAC-1990-Fishburn #heuristic #how #logic
- A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between (JPF), pp. 361–364.
