BibSLEIGH corpus
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Used together with:
base (13)
map (9)
technolog (7)
fpga (7)
fpgas (4)

Stem lut$ (all stems)

16 papers:

DATEDATE-2015-KumarAL #detection #fault #monitoring
Operational fault detection and monitoring of a memristor-based LUT (TNK, HAFA, FL), pp. 429–434.
Mapping into LUT structures (SR, AM, NE, RKB, SJ, CC), pp. 1579–1584.
DATEDATE-2011-RoyRM #algorithm #modelling #performance
Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs (SSR, CR, DM), pp. 1231–1236.
DACDAC-2010-CongM #reliability
LUT-based FPGA technology mapping for reliability (JC, KM), pp. 517–522.
DRRDRR-2009-Obafemi-AjayiAF #classification #documentation #image #performance
Efficient shape-LUT classification for document image restoration (TOA, GA, OF), pp. 1–10.
HCIDHM-2009-JeonJKH #classification #gender #using
Facial Gender Classification Using LUT-Based Sub-images and DIE (JBJ, SHJ, DJK, KSH), pp. 36–45.
DRRDRR-2008-Obafemi-AjayiAF #classification #documentation
Ensemble LUT classification for degraded document enhancement (TOA, GA, OF), p. 681509.
DATEDATE-DF-2006-VeredasSP #automation #performance
Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time (FJV, MS, HJP), pp. 36–41.
DATEDATE-2002-AbkeB #automaton #implementation
A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs (JA, EB), p. 1085.
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs (JC, SX), pp. 704–707.
DACDAC-1998-KorupoluLW #independence #logic
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs (MRK, KKL, DFW), pp. 708–711.
DACDAC-1998-KumthekarBMS #optimisation
In-Place Power Optimization for LUT-Based FPGAs (BK, LB, EM, FS), pp. 718–721.
DACDAC-1996-CongH #composition #design
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design (JC, YYH), pp. 726–729.
DACDAC-1996-LeglWE #approach #design
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs (CL, BW, KE), pp. 730–733.
DACDAC-1995-ShenHC #composition #set
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping (WZS, JDH, SMC), pp. 65–69.
DACDAC-1993-CongD #on the #trade-off
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping (JC, YD), pp. 213–218.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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