16 papers:
CASE-2015-YuYS #multi- Motion planning and manipulation of multiple nanowires simultaneouly under electric-fields in fluid suspension (KY, JY, JS), pp. 489–494.
DAC-2015-SuC #complexity- Nanowire-aware routing considering high cut mask complexity (YHS, YWC), p. 6.
DATE-2015-MohammadiGM #fault #modelling- Fault modeling in controllable polarity silicon nanowire circuits (HGM, PEG, GDM), pp. 453–458.
- DATE-2014-SchmidBMKSKMSR
- III-V semiconductor nanowires for future devices (HS, BMB, KM, PDK, GS, SFK, PM, VS, HR), pp. 1–2.
- DATE-2014-WangYSK #encryption #energy #in memory #performance
- Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire (YW, HY, DS, PK), pp. 1–4.
- DATE-2014-WeberTGHKM #challenge #configuration management
- Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges (WMW, JT, MG, AH, MK, TM), pp. 1–6.
- CASE-2013-YuLYS
- Electrophoresis-based motion planning and control of a nanowire in fluid suspension (KY, XL, JY, JS), pp. 819–824.
- DAC-2013-GaillardonMABSLM #towards #using
- Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.
- DATE-2013-GaillardonABMSLM
- Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs (PEG, LGA, SB, MDM, DS, YL, GDM), pp. 625–630.
- DAC-2012-BobbaMLM #physics #synthesis
- Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.
- DAC-2011-SternRVRCPFR
- CMOS compatible nanowires for biosensing (ES, DAR, AV, NKR, JMC, JP, TMF, MR), pp. 718–722.
- CASE-2010-RuZSZSHC #automation #metric
- Automated four-point probe measurement of nanowires inside a scanning electron microscope (CR, YZ, YS, YZ, XS, DH, IC), pp. 533–538.
- DAC-2009-JamaaLM #array #multi
- Decoding nanowire arrays fabricated with the multi-spacer patterning technique (MHBJ, YL, GDM), pp. 77–82.
- DATE-2009-ZhengH #array #logic #programmable #satisfiability
- Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability (YZ, CH), pp. 1279–1283.
- DATE-2008-DongZ #integration #logic #standard #synthesis
- Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration (MD, LZ), pp. 268–271.
- DAC-2006-RaoOK #architecture #logic
- Topology aware mapping of logic functions onto nanowire-based crossbar architectures (WR, AO, RK), pp. 723–726.
