13 papers:
DAC-2014-XiangQZLYSL #generative- Row Based Dual-VDD Island Generation and Placement (HX, HQ, CZ, YSL, FY, AS, PFL), p. 6.
DATE-2014-VartziotisKCPJ #multi #optimisation #using- Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing (FV, XK, KC, RAP, AJ), pp. 1–6.
- DATE-2013-SureshYOS #adaptation #multi #reduction
- Adaptive reduction of the frequency search space for multi-vdd digital circuits (CKHS, EY, SO, OS), pp. 292–295.
- DATE-2009-KimYK #online #runtime #scalability
- Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling (JK, SY, CMK), pp. 417–422.
- DAC-2008-BijanskyA #named
- TuneFPGA: post-silicon tuning of dual-Vdd FPGAs (SB, AA), pp. 796–799.
- DATE-2007-LinH #interactive #reduction #statistics
- Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction (YL, LH), pp. 636–641.
- DAC-2006-HuLHT #reduction
- Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction (YH, YL, LH, TT), pp. 478–483.
- DATE-2006-GandhiM #energy #multi #using
- Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits (KRG, NRM), pp. 1001–1006.
- DAC-2005-LinH #performance #reduction
- Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction (YL, LH), pp. 720–725.
- DAC-2005-TamH
- Power optimal dual-Vdd buffered tree considering buffer stations and blockages (KHT, LH), pp. 497–502.
- DAC-2004-LiLH #configuration management #reduction #using
- FPGA power reduction using configurable dual-Vdd (FL, YL, LH), pp. 735–740.
- DAC-2004-SrivastavaSB04a #power management #using
- Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment (AS, DS, DB), pp. 783–787.
- DATE-v1-2004-SrivastavaSB #concurrent #design #power management
- Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design (AS, DS, DB), pp. 718–719.
