Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain
A gate level model for CMOS combinational logic circuits with application to fault detection
DAC, 1984.
@inproceedings{DAC-1984-ReddyAJ,
acmid = "800846",
author = "Sudhakar M. Reddy and Vishwani D. Agrawal and Sunil K. Jain",
booktitle = "{Proceedings of the 21st Design Automation Conference}",
isbn = "0-8186-0542-1",
pages = "504--509",
publisher = "{ACM/IEEE}",
title = "{A gate level model for CMOS combinational logic circuits with application to fault detection}",
year = 1984,
}