BibSLEIGH corpus
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Open Knowledge
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Travelled to:
2 × USA
Collaborated with:
V.D.Agrawal A.K.Susskind S.M.Reddy
Talks about:
circuit (2) fault (2) test (2) microprocess (1) algorithm (1) strategi (1) generat (1) stafan (1) detect (1) combin (1)

Person: Sunil K. Jain

DBLP DBLP: Jain:Sunil_K=

Contributed to:

DAC 19841984
DAC 19831983

Wrote 4 papers:

DAC-1984-JainA #fault #named #simulation
STAFAN: An alternative to fault simulation (SKJ, VDA), pp. 18–23.
DAC-1984-ReddyAJ #detection #fault #logic
A gate level model for CMOS combinational logic circuits with application to fault detection (SMR, VDA, SKJ), pp. 504–509.
DAC-1983-JainA #generative #testing #using
Test generation for MOS circuits using D-algorithm (SKJ, VDA), pp. 64–70.
Test strategy for microprocessers (SKJ, AKS), pp. 703–708.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.