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Travelled to:
2 × USA
3 × France
3 × Germany
Collaborated with:
W.Rosenstiel O.Bringmann M.Pressler T.Schönwald J.Schnerr Tobias Hoppe Harald Eisenmann Oliver Bringmann 0001 A.Burger T.Nirmaier M.Harrant G.Pelz S.Lämmermann J.Ruf T.Kropf A.Jesser L.Hedrich J.Oetjens N.Bannow M.Becker M.Chaari S.Chakraborty R.Drechsler W.Ecker K.Grüttner T.Kruse C.Kuznik H.M.Le M.Mauderer W.Müller D.Müller-Gritschneder F.Poppen H.Post S.Reiter S.Roth U.Schlichtmann A.v.Schwerin B.Tabacaru
Talks about:
softwar (4) perform (3) system (3) automot (2) analysi (2) design (2) deploy (2) simul (2) model (2) embed (2)

Person: Alexander Viehl

DBLP DBLP: Viehl:Alexander

Contributed to:

CBSE 20142014
DAC 20142014
DATE 20142014
DATE 20132013
DATE 20102010
DATE 20092009
DAC 20082008
DATE 20062006
ICSA 20172017

Wrote 9 papers:

CBSE-2014-PresslerVBR #component #deployment #embedded #estimation #execution
Execution cost estimation for software deployment in component-based embedded systems (MP, AV, OB, WR), pp. 123–128.
DAC-2014-OetjensBBBBCCDEGKKLM0MPPRRRSSTV #challenge #evaluation #prototype #research #safety #state of the art #using
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges (JHO, NB, MB, OB, AB, MC, SC, RD, WE, KG, TK, CK, HML, MM, WM, DMG, FP, HP, SR, WR, SR, US, AvS, BAT, AV), p. 6.
DATE-2014-NirmaierBHVBRP #assessment #robust
Mission profile aware robustness assessment of automotive power devices (TN, AB, MH, AV, OB, WR, GP), pp. 1–6.
DATE-2013-SchonwaldVBR #deployment #memory management
Shared memory aware MPSoC software deployment (TS, AV, OB, WR), pp. 1771–1776.
DATE-2010-LammermannRKRVJH #design #towards #verification
Towards assertion-based verification of heterogeneous system designs (SL, JR, TK, WR, AV, AJ, LH), pp. 1171–1176.
DATE-2009-ViehlPBR #analysis #performance #scheduling
White box performance analysis considering static non-preemptive software scheduling (AV, MP, OB, WR), pp. 513–518.
DAC-2008-SchnerrBVR #embedded #simulation
High-performance timing simulation of embedded software (JS, OB, AV, WR), pp. 290–295.
DATE-2006-ViehlSBR #analysis #design #modelling #performance #simulation #uml
Formal performance analysis and simulation of UML/SysML models for ESL design (AV, TS, OB, WR), pp. 242–247.
ICSA-2017-HoppeEVB #modelling #semantics
Digital Space Systems Engineering through Semantic Data Models (TH, HE, AV, OB0), pp. 93–96.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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