BibSLEIGH — Lars

Travelled to:

1 × Denmark
3 × Germany
4 × USA
6 × France

Collaborated with:

E.Barke W.Hartong M.Meissner S.Steinhorst F.Salfelder O.Mitea X.Wang R.Popp J.v.Rosen C.Borchers L.Luy P.Jores L.Näthke V.Burkhay J.Oehmen T.Adler H.Brocke M.Kauer S.Naranayaswami M.Lukasiewycz S.Chakraborty S.Lämmermann J.Ruf T.Kropf W.Rosenstiel A.Viehl A.Jesser D.Grabowski H.Gräb S.Heinen Y.Wang

Talks about:

analog (15) circuit (8) model (7) nonlinear (6) system (6) verif (5) base (5) check (4) synthesi (3) approach (3)

Person: Lars Hedrich

DBLP: Hedrich:Lars

Contributed to:

2015

2013

2012

2011

2010

2009

2008

2004

2002

2000

1998

1996

Wrote 17 papers:

DATE-2015-RosenMH #architecture #implementation #multi #reliability: Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog cores (JvR, MM, LH), pp. 912–915.
DATE-2015-SalfelderH #adaptation #evaluation #simulation #using: Ageing simulation of analogue circuits and systems using adaptive transient evaluation (FS, LH), pp. 1261–1264.
DAC-2013-KauerNSLCH #architecture #composition #concurrent: Modular system-level architecture for concurrent cell balancing (MK, SN, SS, ML, SC, LH), p. 10.
DATE-2012-MeissnerMLH #framework #graph #morphism #performance #synthesis #testing: Fast isomorphism testing for a graph-based analog circuit synthesis framework (MM, OM, LL, LH), pp. 757–762.
DATE-2011-MiteaMHJ #automation #constraints #synthesis: Automated constraint-driven topology synthesis for analog circuits (OM, MM, LH, PJ), pp. 1662–1665.
DATE-2010-LammermannRKRVJH #design #towards #verification: Towards assertion-based verification of heterogeneous system designs (SL, JR, TK, WR, AV, AJ, LH), pp. 1171–1176.
DATE-2009-BarkeGGHHPSW #formal method #verification: Formal approaches to analog circuit verification (EB, DG, HG, LH, SH, RP, SS, YW), pp. 724–729.
DATE-2008-SteinhorstH #model checking #specification #using: Model Checking of Analog Systems using an Analog Specification Language (SS, LH), pp. 324–329.
DATE-2008-WangH #multi #synthesis: Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology (XW, LH), pp. 800–803.
DATE-v1-2004-NathkeBHB #automation #behaviour #generative: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques (LN, VB, LH, EB), pp. 442–447.
CAV-2002-HartongHB #model checking #modelling #on the: On Discrete Modeling and Model Checking for Nonlinear Analog Systems (WH, LH, EB), pp. 401–413.
DAC-2002-HartongHB #algorithm #model checking #verification: Model checking algorithms for analog verification (WH, LH, EB), pp. 542–547.
DATE-2002-HartongHB #approach #model checking: An Approach to Model Checking for Nonlinear Analog Systems (WH, LH, EB), p. 1080.
DATE-2002-PoppOHB #analysis #automation #parametricity: Parameter Controlled Automatic Symbolic Analysis of Nonlinear Analog Circuits (RP, JO, LH, EB), pp. 274–278.
DAC-2000-AdlerBHB #verification: A current driven routing and verification methodology for analog applications (TA, HB, LH, EB), pp. 385–389.
DATE-1998-HedrichB #approach #formal method #linear #parametricity #verification: A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances (LH, EB), pp. 649–654.
DAC-1996-BorchersHB #behaviour #equation #generative: Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits (CB, LH, EB), pp. 236–239.