BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
2 × USA
4 × Germany
Collaborated with:
E.J.Marinissen F.Hapke B.Vermeulen M.Z.Urfianto A.Sehgal K.Chakrabarty H.P.E.Vranken A.Glowatz J.Schlöffel K.Chiu T.Nguyen S.Oostdijk G.Vandling J.Rivers N.Mittermaier S.Bahl
Talks about:
test (7) design (4) chip (4) infrastructur (3) system (3) detect (2) architectur (1) breakpoint (1) technolog (1) hierarchi (1)

Person: Sandeep Kumar Goel

DBLP DBLP: Goel:Sandeep_Kumar

Contributed to:

DATE 20122012
DAC 20062006
DATE 20062006
DATE 20052005
DAC 20042004
DATE DF 20042004
DATE 20032003

Wrote 7 papers:

DATE-2012-MarinissenVGHRMB #detection #process
EDA solutions to new-defect detection in advanced process technologies (EJM, GV, SKG, FH, JR, NM, SB), pp. 123–128.
DAC-2006-VrankenGGSH #detection #fault
Fault detection and diagnosis with parity trees for space compaction of test responses (HPEV, SKG, AG, JS, FH), pp. 1095–1098.
DATE-2006-SehgalGMC #design #framework
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips (AS, SKG, EJM, KC), pp. 285–290.
DATE-2005-GoelM #design #framework #multi #testing
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips (SKG, EJM), pp. 44–49.
DAC-2004-VermeulenUG #automation #debugging #generative #hardware
Automatic generation of breakpoint hardware for silicon debug (BV, MZU, SKG), pp. 514–517.
DATE-DF-2004-GoelCMNO #design #framework
Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip (SKG, KC, EJM, TN, SO), pp. 108–113.
DATE-2003-GoelM #architecture #design
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization (SKG, EJM), pp. 10738–10741.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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