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Travelled to:
4 × USA
Collaborated with:
J.Cong S.K.Lim H.Li
Talks about:
retim (4) perform (2) circuit (2) partit (2) optim (2) fpga (2) synthesi (1) simultan (1) sequenti (1) multiway (1)

Person: Chang Wu


Contributed to:

DAC 20002000
DAC 19991999
DAC 19981998
DAC 19971997

Wrote 4 papers:

DAC-2000-CongLW #clustering #multi #performance
Performance driven multi-level and multiway partitioning with retiming (JC, SKL, CW), pp. 274–279.
DAC-1999-CongLW #clustering #optimisation #performance
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization (JC, HL, CW), pp. 460–465.
DAC-1998-CongW #performance
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation (JC, CW), pp. 330–335.
DAC-1997-CongW #pipes and filters #synthesis
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (JC, CW), pp. 644–649.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.