BibSLEIGH — FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits

Jason Cong, Chang Wu
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits
DAC, 1997.

DAC 1997

@inproceedings{DAC-1997-CongW,
	author        = "Jason Cong and Chang Wu",
	booktitle     = "{Proceedings of the 34th Design Automation Conference}",
	doi           = "10.1145/266021.266309",
	isbn          = "0-89791-920-3",
	pages         = "644--649",
	publisher     = "{ACM Press}",
	title         = "{FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits}",
	year          = 1997,
}

Jason Cong, Chang WuFPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential CircuitsDAC, 1997.

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Jason Cong, Chang Wu
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits
DAC, 1997.