Travelled to:1 × France
1 × Israel
1 × Russia
1 × The Netherlands
5 × USA
Collaborated with:I.Beer S.Ben-David D.Fisman Y.Rodeh J.Havlicek A.McIsaac D.V.Campenhout A.Landver O.Adler T.Veksler E.Arbel O.Rokhlenko A.Nahir K.Yorav Y.Lustig A.Gringauze I.Shitsevalov R.Hoover W.G.Nation K.L.Nelson K.Valk D.Geist L.Gluhovsky T.Heyman P.Paanah G.Ronin Y.Wolfsthal
Talks about:tempor (3) function (2) reason (2) formal (2) design (2) verif (2) logic (2) clock (2) rule (2) gate (2)
Person: Cindy Eisner
DBLP: Eisner:Cindy
Contributed to:
2013
200920082003
20032001200019971996Wrote 10 papers:
- CAV-2013-AdlerEV #ambiguity #equivalence
- Relative Equivalence in the Presence of Ambiguity (OA, CE, TV), pp. 430–446.
- DAC-2009-ArbelER
- Resurrecting infeasible clock-gating functions (EA, CE, OR), pp. 160–165.
- CAV-2008-EisnerNY #composition #design #functional #power management #reasoning #verification
- Functional Verification of Power Gated Designs by Compositional Reasoning (CE, AN, KY), pp. 433–445.
- CAV-2003-EisnerFHLMC #logic #reasoning
- Reasoning with Temporal Logic on Truncated Paths (CE, DF, JH, YL, AM, DVC), pp. 27–39.
- ICALP-2003-EisnerFHMC
- The Definition of a Temporal Clock Operator (CE, DF, JH, AM, DVC), pp. 857–870.
- CAV-2001-BeerBEFGR #logic
- The Temporal Logic Sugar (IB, SBD, CE, DF, AG, YR), pp. 363–367.
- DAC-2000-EisnerSHNNV #design #hardware #protocol
- A methodology for formal design of hardware control with application to cache coherence protocols (CE, IS, RH, WGN, KLN, KV), pp. 724–729.
- CAV-1997-BeerBEGGHLPRRW #model checking #named
- RuleBase: Model Checking at IBM (IB, SBD, CE, DG, LG, TH, AL, PP, YR, GR, YW), pp. 480–483.
- CAV-1997-BeerBER #detection #performance
- Efficient Detection of Vacuity in ACTL Formulaas (IB, SBD, CE, YR), pp. 279–290.
- DAC-1996-BeerBEL #named #verification
- RuleBase: An Industry-Oriented Formal Verification Tool (IB, SBD, CE, AL), pp. 655–660.