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Travelled to:
1 × Germany
1 × India
1 × Ireland
1 × Italy
1 × United Kingdom
9 × USA
Collaborated with:
V.Sridharan A.Aletà J.M.Codina A.González K.Ning J.Kalamatianos R.Whelan T.Leek J.Mankin J.Ardini J.Black E.Melachrinoudis A.H.Hashemi B.Calder D.Schaa P.Mistry H.Asadi M.B.Tahoori K.Sanghai T.Su J.G.Dy B.Jang R.Dominguez Yifan Sun Chisheng Liang S.C.Sutherland C.Harteveld H.Wu B.Salzberg G.C.Sharp S.B.Jiang H.Shirato R.Ubal X.Gong Y.Ukidave Z.Chen G.Schirner
Talks about:
architectur (4) model (3) data (3) cach (3) microarchitectur (2) heterogen (2) procedur (2) perform (2) cluster (2) vulner (2)

Person: David R. Kaeli

DBLP DBLP: Kaeli:David_R=

Facilitated 2 volumes:

CGO 2014Ed
CGO 2010Ed

Contributed to:

DAC 20142014
CC 20132013
PPoPP 20102010
HPCA 20092009
LCTES 20092009
CGO 20072007
LCTES 20072007
DATE 20062006
KDD 20052005
PLDI 20052005
SIGMOD 20052005
ICSE 20042004
HPCA 19981998
PLDI 19971997
CIG 20162016

Wrote 15 papers:

DAC-2014-UbalSMGUCSK #design #performance #reliability
Exploring the Heterogeneous Design Space for both Performance and Reliability (RU, DS, PM, XG, YU, ZC, GS, DRK), p. 6.
CC-2013-WhelanLK #architecture #data flow #independence #information management
Architecture-Independent Dynamic Information Flow Tracking (RW, TL, DRK), pp. 144–163.
PPoPP-2010-JangMSDK #architecture #data transformation #parallel #thread
Data transformations enabling loop vectorization on multithreaded data parallel architectures (BJ, PM, DS, RD, DRK), pp. 353–354.
HPCA-2009-SridharanK #architecture #dependence
Eliminating microarchitectural dependency from Architectural Vulnerability (VS, DRK), pp. 117–128.
LCTES-2009-MankinKA #embedded #manycore #memory management #transaction
Software transactional memory for multicore embedded systems (JM, DRK, JA), pp. 90–98.
CGO-2007-AletaCGK #architecture #clustering
Heterogeneous Clustered VLIW Microarchitectures (AA, JMC, AG, DRK), pp. 354–366.
LCTES-2007-NingK #embedded #memory management #multi
External memory page remapping for embedded multimedia systems (KN, DRK), pp. 185–194.
DATE-2006-AsadiSTK #analysis
Vulnerability analysis of L2 cache elements to single event upsets (HA, VS, MBT, DRK), pp. 1276–1281.
KDD-2005-SanghaiSDK #architecture #clustering #design #multi #performance #simulation
A multinomial clustering model for fast simulation of computer architecture designs (KS, TS, JGD, DRK), pp. 808–813.
PLDI-2005-AletaCGK #on the fly
Demystifying on-the-fly spill code (AA, JMC, AG, DRK), pp. 180–189.
SIGMOD-2005-WuSSJSK #sequence
Subsequence Matching on Structured Time Series Data (HW, BS, GCS, SBJ, HS, DRK), pp. 682–693.
ICSE-2004-BlackMK #modelling #reduction #testing
Bi-Criteria Models for All-Uses Test Suite Reduction (JB, EM, DRK), pp. 106–115.
HPCA-1998-KalamatianosK #order #performance
Temporal-Based Procedure Reordering for Improved Instruction Cache Performance (JK, DRK), pp. 244–253.
PLDI-1997-HashemiKC #performance #using
Efficient Procedure Mapping Using Cache Line Coloring (AHH, DRK, BC), pp. 171–182.
CIG-2016-SunLSHK #game studies #modelling
Modeling player decisions in a supply chain game (YS, CL, SCS, CH, DRK), pp. 1–8.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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