Travelled to:5 × USA
Collaborated with:J.York N.A.Patil A.Bansal M.Pellauer M.Adler J.S.Emer P.Jain L.Rudolph S.Devadas Dan Zhang 0004 Xiaoyu Ma Michael Thomson G.Y.Wu J.L.Greathouse A.Lyashevsky N.Jayasena
Talks about:worklist (2) manag (2) use (2) lightweight (1) architectur (1) reconfigur (1) multiplex (1) synthesi (1) prefetch (1) contract (1)
Person: Derek Chiou
DBLP: Chiou:Derek
Contributed to:
2015
2012201120092000
2018Wrote 6 papers:
- HPCA-2015-WuGLJC #estimation #machine learning #performance #using
- GPGPU performance and power estimation using machine learning (GYW, JLG, AL, NJ, DC), pp. 564–576.
- DAC-2012-YorkC #multi #on the
- On the asymptotic costs of multiplexer-based reconfigurability (JY, DC), pp. 790–795.
- DAC-2011-PatilBC #architecture #contract #synthesis
- Enforcing architectural contracts in high-level synthesis (NAP, AB, DC), pp. 824–829.
- DAC-2009-PellauerACE #composition #problem
- Soft connections: addressing the hardware-design modularity problem (MP, MA, DC, JSE), pp. 276–281.
- DAC-2000-ChiouJRD #embedded #memory management #using
- Application-specific memory management for embedded systems using software-controlled caches (DC, PJ, LR, SD), pp. 416–419.
- ASPLOS-2018-0004MTC #lightweight #named
- Minnow: Lightweight Offload Engines for Worklist Management and Worklist-Directed Prefetching (DZ0, XM, MT, DC), pp. 593–607.