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Travelled to:
2 × Germany
4 × USA
Collaborated with:
Y.I.Ismail J.L.Neves M.C.Papaefthymiou X.Liu S.Köse D.Velenis
Talks about:
delay (4) perform (3) clock (3) schedul (2) circuit (2) variat (2) induct (2) skew (2) high (2) uncertainti (1)

Person: Eby G. Friedman

DBLP DBLP: Friedman:Eby_G=

Contributed to:

DAC 20112011
DATE 20032003
DAC 19991999
DATE 19991999
DAC 19981998
DAC 19961996

Wrote 8 papers:

DAC-2011-KoseF #algorithm #analysis #information retrieval #locality #performance
Fast algorithms for IR voltage drop analysis exploiting locality (SK, EGF), pp. 996–1001.
DATE-2003-VelenisPF #network #nondeterminism #performance
Reduced Delay Uncertainty in High Performance Clock Distribution Networks (DV, MCP, EGF), pp. 10068–10075.
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits (YII, EGF), pp. 721–724.
Equivalent Elmore Delay for RLC Trees (YII, EGF, JLN), pp. 715–720.
DAC-1999-LiuPF #performance #scheduling
Maximizing Performance by Retiming and Clock Skew Scheduling (XL, MCP, EGF), pp. 231–236.
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (XL, MCP, EGF), pp. 643–649.
Figures of Merit to Characterize the Importance of On-Chip Inductance (YII, EGF, JLN), pp. 560–565.
DAC-1996-NevesF #process #scheduling
Optimal Clock Skew Scheduling Tolerant to Process Variations (JLN, EGF), pp. 623–628.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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