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Travelled to:
1 × China
3 × Germany
6 × USA
Collaborated with:
M.C.Papaefthymiou Y.Peng E.G.Friedman Z.Yu L.Wu X.Meng S.Chen
Talks about:
power (6) repeat (5) insert (4) low (4) design (3) perform (2) circuit (2) method (2) minim (2) delay (2)

Person: Xun Liu


Contributed to:

DAC 20072007
DAC 20062006
ICPR v1 20062006
DAC 20052005
DATE 20052005
DAC 20042004
DAC 20022002
DATE 20012001
DAC 19991999
DATE 19991999

Wrote 10 papers:

DAC-2007-YuL #design
Design of Rotary Clock Based Circuits (ZY, XL), pp. 43–48.
DAC-2006-PengL #constraints #power management
Low-power repeater insertion with both delay and slew rate constraints (YP, XL), pp. 302–307.
ICPR-v1-2006-WuMLC #segmentation
A New Method of Object Segmentation in the Basketball Videos (LW, XM, XL, SC), pp. 319–322.
DAC-2005-PengL #named #performance #power management #using
Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method (YP, XL), pp. 813–818.
DATE-2005-LiuPP #hybrid #named #performance #power management
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power (XL, YP, MCP), pp. 1330–1335.
DAC-2004-LiuPP #library #power management #question #what
Practical repeater insertion for low power: what repeater library do we need? (XL, YP, MCP), pp. 30–35.
DAC-2002-LiuP #design #power management
Design of a high-throughput low-power IS95 Viterbi decoder (XL, MCP), pp. 263–268.
DATE-2001-LiuP #design #estimation
A static power estimation methodolodgy for IP-based design (XL, MCP), pp. 280–289.
DAC-1999-LiuPF #performance #scheduling
Maximizing Performance by Retiming and Clock Skew Scheduling (XL, MCP, EGF), pp. 231–236.
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (XL, MCP, EGF), pp. 643–649.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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