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Travelled to:
2 × Germany
2 × USA
Collaborated with:
L.Benini P.Marchal G.Paci A.Poggiali D.Bertozzi D.Atienza J.M.Mendias S.Künzli L.Thiele M.Ruggiero A.Guerri M.Milano F.Catthoor P.G.D.Valle G.D.Micheli I.A.Khatib M.Bechara H.Khalifeh A.Jantsch R.Nabiev
Talks about:
system (4) chip (3) architectur (2) processor (2) framework (2) softwar (2) hardwar (2) analysi (2) explor (2) design (2)

Person: Francesco Poletti

DBLP DBLP: Poletti:Francesco

Contributed to:

DAC 20062006
DATE 20062006
DATE 20052005
DAC 20042004

Wrote 7 papers:

DAC-2006-AtienzaVPPBMM #framework #multi #performance
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip (DA, PGDV, GP, FP, LB, GDM, JMM), pp. 618–623.
DAC-2006-KhatibPBBBKJN #analysis #architecture #design #monitoring #multi #realtime
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration (IAK, FP, DB, LB, MB, HK, AJ, RN), pp. 125–130.
DATE-2006-KunzliPBT #analysis #formal method #performance #simulation
Combining simulation and formal methods for system-level performance analysis (SK, FP, LB, LT), pp. 236–241.
DATE-2006-PaciMPB #design #power management
Exploring “temperature-aware” design in low-power MPSoCs (GP, PM, FP, LB), pp. 838–843.
DATE-2006-RuggieroGBPM #framework #multi #scheduling
Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip (MR, AG, DB, FP, MM), pp. 3–8.
DATE-2005-FrancescoAM #architecture #distributed #flexibility #hardware #memory management #message passing
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture (FP, AP, PM), pp. 736–741.
DAC-2004-FrancescoMABCM #approach #hardware #runtime
An integrated hardware/software approach for run-time scratchpad management (FP, PM, DA, LB, FC, JMM), pp. 238–243.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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