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Travelled to:
1 × France
1 × USA
Collaborated with:
J.Cong Y.Shi J.Shin J.A.Darringer A.J.Weger C.L.Johnson
Talks about:
placement (1) thermal (1) silicon (1) cockpit (1) earli (1) plan (1) chip (1) cell (1) awar (1)

Person: Guojie Luo

DBLP DBLP: Luo:Guojie

Contributed to:

DAC 20112011
DATE 20112011

Wrote 2 papers:

DAC-2011-CongLS #3d
Thermal-aware cell and through-silicon-via co-placement for 3D ICs (JC, GL, YS), pp. 670–675.
DATE-2011-ShinDLWJ
Early chip planning cockpit (JS, JAD, GL, AJW, CLJ), pp. 863–866.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.