BibSLEIGH corpus
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Travelled to:
1 × France
1 × Germany
5 × USA
Collaborated with:
W.H.J.Jr. J.Shin A.J.Weger G.Luo C.L.Johnson S.Rawat D.Gajski P.O.Pistilli H.D.Man C.Harris J.Solomon P.Bose A.Buyuktosunoglu M.S.Gupta M.B.Healy H.M.Jacobson I.Nair J.A.Rivers A.Vega
Talks about:
challeng (2) verif (2) multi (2) good (2) core (2) chip (2) processor (1) techniqu (1) synthesi (1) descript (1)

Person: John A. Darringer

DBLP DBLP: Darringer:John_A=

Contributed to:

DATE 20122012
DATE 20112011
DAC 20072007
DAC 20042004
DAC 19801980
DAC 19791979
DAC 19681968

Wrote 7 papers:

DATE-2012-BoseBDGHJNRSVW #challenge #manycore #power management
Power management of multi-core chips: Challenges and pitfalls (PB, AB, JAD, MSG, MBH, HMJ, IN, JAR, JS, AV, AJW), pp. 977–982.
Early chip planning cockpit (JS, JAD, GL, AJW, CLJ), pp. 863–866.
DAC-2007-Darringer #automation #challenge #design #manycore
Multi-Core Design Automation Challenges (JAD), pp. 760–764.
Were the good old days all that good?: EDA then and now (SR, WHJJ, JAD, DG, POP, HDM, CH, JS), p. 543.
DAC-1980-DarringerJ #logic #synthesis
A new look at logic synthesis (JAD, WHJJ), pp. 543–549.
DAC-1979-Darringer #hardware #verification
The application of program verification techniques to hardware verification (JAD), pp. 375–381.
A language for the description of digital computer processors (JAD).

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.