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Travelled to:
1 × France
4 × USA
Collaborated with:
D.F.Wong X.Tang M.Cho R.Puri H.Ren D.Z.Pan L.Huang I.Liu H.Qian C.Zhou Y.Lin F.Yee A.Sullivan P.Lu
Talks about:
algorithm (2) plan (2) base (2) placement (1) polynomi (1) problem (1) network (1) histori (1) generat (1) antenna (1)

Person: Hua Xiang

DBLP DBLP: Xiang:Hua

Contributed to:

DAC 20142014
DAC 20102010
DAC 20072007
DAC 20022002
DATE 20022002

Wrote 5 papers:

DAC-2014-XiangQZLYSL #generative
Row Based Dual-VDD Island Generation and Placement (HX, HQ, CZ, YSL, FY, AS, PFL), p. 6.
DAC-2010-ChoRXP #network #using
History-based VLSI legalization using network flow (MC, HR, HX, RP), pp. 286–291.
DAC-2007-ChoXPP #named
TROY: Track Router with Yield-driven Wire Planning (MC, HX, RP, DZP), pp. 55–58.
DAC-2002-XiangWT #algorithm
An algorithm for integrated pin assignment and buffer planning (HX, DFW, XT), pp. 584–589.
DATE-2002-HuangTXWL #algorithm #polynomial #problem
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem (LDH, XT, HX, DFW, IML), pp. 470–475.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.