BibSLEIGH corpus
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Travelled to:
2 × France
2 × USA
Collaborated with:
D.F.Wong A.Aziz H.Wu M.D.F.Wong H.Zhou L.Huang X.Tang H.Xiang
Talks about:
insert (3) voltag (2) buffer (2) time (2) rout (2) constraint (1) constrain (1) algorithm (1) simultan (1) restrict (1)

Person: I-Min Liu


Contributed to:

DAC 20062006
DATE 20022002
DATE 20002000
DAC 19991999

Wrote 4 papers:

Timing-constrained and voltage-island-aware voltage assignment (HW, MDFW, IML), pp. 429–432.
DATE-2002-HuangTXWL #algorithm #polynomial #problem
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem (LDH, XT, HX, DFW, IML), pp. 470–475.
DATE-2000-LiuAW #constraints
Meeting Delay Constraints in DSM by Minimal Repeater Insertion (IML, AA, DFW), pp. 436–440.
DAC-1999-ZhouWLA #strict
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations (HZ, DFW, IML, AA), pp. 96–99.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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