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Travelled to:
1 × Belgium
1 × Canada
1 × France
1 × Italy
12 × USA
2 × Israel
Collaborated with:
V.Singhal R.K.Brayton F.Balarin T.R.Shiple F.A.Zaraket S.Khurshid I.Liu D.F.Wong S.Bijansky J.Yuan J.Baumgartner H.Zhou K.Sajid S.Tasiran A.L.Sangiovanni-Vincentelli P.Yalagandula M.K.Ganai A.Kuehlmann J.H.Kukula Y.Luo T.Wongsonegoro M.Mohiyuddin A.Prakash W.Wolf K.Albin C.Pixley T.Heyman J.Shen J.A.Abraham T.Liu K.Sanwal A.Tripp F.Andersen A.Goel M.D.DiBenedetto A.Saldanha S.Cheng R.K.Ranjan R.Hojati T.Kam S.C.Krishnan H.Wang G.D.Hachtel F.Somenzi S.A.Edwards S.P.Khatri Y.Kukimoto A.Pardo S.Qadeer S.Sarwary G.Swamy T.Villa
Talks about:
verif (6) function (3) state (3) simul (3) model (3) check (3) bdd (3) constraint (2) algorithm (2) synthesi (2)

Person: Adnan Aziz

DBLP DBLP: Aziz:Adnan

Contributed to:

DAC 20082008
ASE 20072007
ICSE 20072007
DAC 20042004
DAC 20032003
CAV 20002000
DATE 20002000
CAV 19991999
DAC 19991999
CAV 19981998
DAC 19981998
CAV 19971997
DAC 19971997
CAV 19961996
CAV 19951995
CAV 19941994
DAC 19941994
ICALP 19941994

Wrote 24 papers:

DAC-2008-BijanskyA #named
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs (SB, AA), pp. 796–799.
ASE-2007-ZaraketAK #program analysis
Sequential circuits for program analysis (FAZ, AA, SK), pp. 114–123.
ICSE-2007-ZaraketAK #analysis #relational
Sequential Circuits for Relational Analysis (FAZ, AA, SK), pp. 13–22.
Synthesizing interconnect-efficient low density parity check codes (MM, AP, AA, WW), pp. 488–491.
DAC-2003-YuanAAP #constraints #functional #modelling #synthesis #verification
Constraint synthesis for environment modeling in functional verification (JY, KA, AA, CP), pp. 296–299.
CAV-2000-BaumgartnerTASA #abstraction #algorithm #design #verification
An Abstraction Algorithm for the Verification of Generalized C-Slow Designs (JB, AT, AA, VS, FA), pp. 5–19.
DATE-2000-LiuAW #constraints
Meeting Delay Constraints in DSM by Minimal Repeater Insertion (IML, AA, DFW), pp. 436–440.
DATE-2000-YalagandulaAS #automation #generative
Automatic Lighthouse Generation for Directed State Space Search (PY, AA, VS), pp. 237–242.
CAV-1999-BaumgartnerHSA #abstraction #algorithm #model checking
Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists (JB, TH, VS, AA), pp. 72–83.
DAC-1999-GanaiAK #simulation
Enhancing Simulation with BDDs and ATPG (MKG, AA, AK), pp. 385–390.
DAC-1999-ZhouWLA #strict
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations (HZ, DFW, IML, AA), pp. 96–99.
CAV-1998-GoelSZAS #formal method #similarity
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions (AG, KS, HZ, AA, VS), pp. 244–255.
DAC-1998-AzizKS #hybrid #simulation #using #verification
Hybrid Verification Using Saturated Simulation (AA, JHK, TRS), pp. 615–618.
DAC-1998-LuoWA #functional #hybrid #performance #simulation
Hybrid Techniques for Fast Functional Simulation (YL, TW, AA), pp. 664–667.
CAV-1997-YuanSAA #on the #verification
On Combining Formal and Informal Verification (JY, JS, JAA, AA), pp. 376–387.
DAC-1997-LiuSAS #black box #design #optimisation
Optimizing Designs Containing Black Boxes (THL, KS, AA, VS), pp. 113–116.
CAV-1996-AzizSSB #markov #verification
Verifying Continuous Time Markov Chains (AA, KS, VS, RKB), pp. 269–276.
CAV-1996-BraytonHSSACEKKPQRSSSV #named #synthesis #verification
VIS: A System for Verification and Synthesis (RKB, GDH, ALSV, FS, AA, STC, SAE, SPK, YK, AP, SQ, RKR, SS, TRS, GS, TV), pp. 428–432.
CAV-1995-AzizBBDS #finite #state machine
Supervisory Control of Finite State Machines (AA, FB, RKB, MDD, AS), pp. 279–292.
CAV-1995-AzizSB #logic #probability
It Usually Works: The Temporal Logic of Stochastic Systems (AA, VS, FB), pp. 155–165.
CAV-1994-AzizSS #composition #equivalence #model checking
Formula-Dependent Equivalence for Compositional CTL Model Checking (AA, TRS, VS), pp. 324–337.
DAC-1994-AzizBCHKKRSSTWBS #named #verification
HSIS: A BDD-Based Environment for Formal Verification (AA, FB, STC, RH, TK, SCK, RKR, TRS, VS, ST, HYW, RKB, ALSV), pp. 454–459.
DAC-1994-AzizTB #finite #state machine
BDD Variable Ordering for Interacting Finite State Machines (AA, ST, RKB), pp. 283–288.
Equivalences for Fair Kripke Structures (AA, VS, FB, RKB, ALSV), pp. 364–375.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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