BibSLEIGH — Martin_D_F

Travelled to:

1 × Germany
1 × United Kingdom
10 × USA
2 × France

Collaborated with:

T.Yan Q.Ma Y.Du H.Zhang L.Cheng D.Chen H.Wu E.Erdem L.Deng H.Kong Y.Chang L.Huang E.F.Y.Young L.Luo W.W.Hwu J.Fang I.Liu V.Lifschitz Z.Xiao H.Yi H.P.Wong R.O.Topaloglu M.P.Lin P.Wu I.Nedelchev S.Bhardwaj V.Parkhe D.Guo M.C.Tung H.Tian H.Song J.Shiely G.Luk-Pat A.Miloslavsky

Talks about:

rout (9) pattern (6) optim (5) algorithm (4) assign (4) self (4) placement (3) voltag (3) doubl (3) awar (3)

Person: Martin D. F. Wong

DBLP: Wong:Martin_D=_F=

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2007

2006

2004

2000

Wrote 23 papers:

DAC-2015-XiaoGWYTW #layout #optimisation #self #verification: Layout optimization and template pattern verification for directed self-assembly (DSA) (ZX, DG, MDFW, HY, MCT, HSPW), p. 6.
DAC-2014-WuWNBP #on the: On Timing Closure: Buffer Insertion for Hold-Violation Removal (PCW, MDFW, IN, SB, VP), p. 6.
DAC-2014-XiaoDTWYWZ #self #verification: Directed Self-Assembly (DSA) Template Pattern Verification (ZX, YD, HT, MDFW, HY, HSPW, HZ), p. 6.
DATE-2014-DuW #optimisation #process #standard: Optimization of standard cell based detailed placement for 16 nm FinFET process (YD, MDFW), pp. 1–6.
DAC-2013-Du0SSLMW #self: Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography (YD, QM, HS, JS, GLP, AM, MDFW), p. 6.
DAC-2012-0002ZW #comparison: Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology (QM, HZ, MDFW), pp. 591–596.
DAC-2011-MaYW #algorithm: An optimal algorithm for layer assignment of bus escape routing on PCBs (QM, EFYY, MDFW), pp. 176–181.
DAC-2011-ZhangDWT #composition #detection #self: Self-aligned double patterning decomposition for overlay minimization and hot spot detection (HZ, YD, MDFW, ROT), pp. 71–76.
DAC-2010-KongMYW #algorithm: An optimal algorithm for finding disjoint rectangles and its application to PCB routing (HK, QM, TY, MDFW), pp. 212–217.
DAC-2010-LuoWH #effectiveness #gpu #implementation: An effective GPU implementation of breadth-first search (LL, MDFW, WmWH), pp. 52–55.
DAC-2009-FangWC #co-evolution #design: Flip-chip routing with unified area-I/O pad assignments for package-board co-design (JWF, MDFW, YWC), pp. 336–339.
DAC-2009-KongYW #automation: Automatic bus planner for dense PCBs (HK, TY, MDFW), pp. 326–331.
DAC-2009-LinZWC: Thermal-driven analog placement considering device matching (MPHL, HZ, MDFW, YWC), pp. 593–598.
DAC-2009-YanW #network: A correct network flow model for escape routing (TY, MDFW), pp. 332–335.
DAC-2007-ChengCW #named #power management: GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches (LC, DC, MDFW), pp. 318–323.
DAC-2007-ChengCW07a #named #synthesis: DDBDD: Delay-Driven BDD Synthesis for FPGAs (LC, DC, MDFW), pp. 910–915.
DAC-2007-WuW #detection #incremental: Improving Voltage Assignment by Outlier Detection and Incremental Placement (HW, MDFW), pp. 459–464.
DAC-2006-ChengDCW #algorithm #generative #performance #power management #reduction: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction (LC, LD, DC, MDFW), pp. 117–120.
DAC-2006-WuWL: Timing-constrained and voltage-island-aware voltage assignment (HW, MDFW, IML), pp. 429–432.
DAC-2004-HuangW #proximity: Optical proximity correction (OPC): friendly maze routing (LDH, MDFW), pp. 186–191.
DATE-v2-2004-DengW #algorithm: Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus (LD, MDFW), pp. 1104–1109.
ICLP-2004-ErdemW #programming #set #using: Rectilinear Steiner Tree Construction Using Answer Set Programming (EE, MDFW), pp. 386–399.
CL-2000-ErdemLW #satisfiability: Wire Routing and Satisfiability Planning (EE, VL, MDFW), pp. 822–836.