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Open Knowledge
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Travelled to:
1 × Portugal
2 × France
4 × Germany
Collaborated with:
M.B.Santos I.C.Teixeira J.M.Fernandes A.L.Oliveira J.T.d.Sousa F.M.Gonçalves T.W.Williams J.C.Vázquez V.H.Champac H.Lérias J.Luz P.Moura A.Mendes Y.Zorian P.Prinetto C.E.Pereira O.P.Dias J.Semião P.Muhmenthaler W.Radermacher
Talks about:
defect (2) level (2) fault (2) embed (2) digit (2) test (2) rtl (2) probabilist (1) determinist (1) construct (1)

Person: João Paulo Teixeira

DBLP DBLP: Teixeira:Jo=atilde=o_Paulo

Contributed to:

DATE 20102010
DATE v1 20042004
DATE 20032003
DATE 20012001
ICEIS v2 20012001
DATE 19991999

Wrote 7 papers:

DATE-2010-VazquezCTST #programmable #safety
Programmable aging sensor for automotive safety-critical applications (JCV, VHC, ICT, MBS, JPT), pp. 618–621.
DATE-v1-2004-FernandesSOT #probability #testing
A Probabilistic Method for the Computation of Testability of RTL Constructs (JMF, MBS, ALO, JPT), pp. 176–181.
DATE-2003-SantosFTT #generative #quality
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST (MBS, JMF, ICT, JPT), pp. 10994–10999.
DATE-2001-ZorianPTTPDSMR #embedded #tutorial
Embedded tutorial: TRP: integrating embedded test and ATE (YZ, PP, JPT, ICT, CEP, OPD, JS, PM, WR), pp. 34–37.
ICEIS-v2-2001-LeriasLMMTT #towards
Towards E-Management as Enabler for Accelerated Change (HL, JL, PM, AM, ICT, JPT), pp. 807–814.
DATE-1999-SantosT #fault #simulation #using
Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL (MBS, JPT), p. 549–?.
EDAC-1994-SousaGTW #fault #modelling
Fault Modeling and Defect Level Projections in Digital ICs (JTdS, FMG, JPT, TWW), pp. 436–442.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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