Travelled to:1 × Germany
6 × USA
Collaborated with:A.Raghunathan S.Dey B.Mochocki S.Cadambi G.Lakshminarayana K.Sekar M.A.Ghodrat P.Stanley-Marbell S.Chandra X.S.Hu
Talks about:system (7) power (6) chip (6) architectur (5) communic (5) perform (3) design (3) high (3) graphic (2) analysi (2)
Person: Kanishka Lahiri
DBLP: Lahiri:Kanishka
Contributed to:
20072006
20062005200220012000Wrote 10 papers:
- DAC-2007-ChandraLRD #power management
- System-on-Chip Power Management Considering Leakage Power Variations (SC, KL, AR, SD), pp. 877–882.
- DAC-2007-GhodratLR #analysis #estimation #hybrid #using
- Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation (MAG, KL, AR), pp. 883–886.
- DAC-2006-MochockiLCH #3d #estimation #mobile
- Signature-based workload estimation for mobile 3D graphics (BM, KL, SC, XSH), pp. 592–597.
- DATE-2006-MochockiLC #3d #analysis #mobile
- Power analysis of mobile 3D graphics (BM, KL, SC), pp. 502–507.
- DATE-2006-SekarLRD #adaptation #configuration management #platform
- Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms (KS, KL, AR, SD), pp. 728–733.
- DATE-2006-Stanley-MarbellLR #adaptation #concurrent #embedded #library #multi #thread
- Adaptive data placement in an embedded multiprocessor thread library (PSM, KL, AR), pp. 698–699.
- DAC-2005-SekarLRD #architecture #communication #configuration management #named
- FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology (KS, KL, AR, SD), pp. 571–574.
- DAC-2002-LahiriDR #architecture #communication #design #performance #power management
- Communication architecture based power management for battery efficient system design (KL, SD, AR), pp. 691–696.
- DAC-2001-LahiriRL #architecture #communication #design #named
- LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs (KL, AR, GL), pp. 15–20.
- DAC-2000-LahiriRLD #architecture #communication #design
- Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips (KL, AR, GL, SD), pp. 513–518.