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Travelled to:
1 × Germany
1 × USA
Collaborated with:
Y.Chen Y.Shi S.Chang T.Wang W.Wen M.Lee W.Hon
Talks about:
threshold (1) dimension (1) constrain (1) monitor (1) circuit (1) voltag (1) integr (1) design (1) degrad (1) critic (1)

Person: Kuan-Yu Lai

DBLP DBLP: Lai:Kuan=Yu

Contributed to:

DAC 20142014
DATE 20142014

Wrote 2 papers:

DAC-2014-ChenWLWSC #design #monitoring #scalability
Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs (YGC, TW, KYL, WYW, YS, SCC), p. 6.
DATE-2014-ChenLLSHC #3d
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits (YGC, KYL, MCL, YS, WKH, SCC), pp. 1–4.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.