Travelled to:3 × France
3 × Germany
Collaborated with:R.S.Khaligh G.Schley W.Putzke-Röming W.Nebel N.Batzolis A.Vörg W.Rosenstiel A.Stammermann M.A.Kochte C.G.Zoellin M.E.Imhof H.Wunderlich S.D.Carlo P.Prinetto
Talks about:model (4) transact (2) accuraci (2) network (2) object (2) simul (2) level (2) fault (2) adapt (2) chip (2)
Person: Martin Radetzki
DBLP: Radetzki:Martin
Contributed to:
20152013
201020092008200419991998Wrote 8 papers:
- PDP-2015-SchleyR #fault tolerance
- Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip (GS, MR), pp. 379–386.
- PDP-2013-SchleyBR #fault #protocol
- Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip (GS, NB, MR), pp. 454–461.
- DATE-2010-KhalighR #adaptation #kernel #modelling #parallel #simulation
- Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs (RSK, MR), pp. 1183–1188.
- DATE-2009-KochteZIKRWCP #modelling #transaction #using #validation
- Test exploration and validation using transaction level models (MAK, CGZ, MEI, RSK, MR, HJW, SDC, PP), pp. 1250–1253.
- DATE-2008-RadetzkiK #adaptation #modelling #simulation #transaction
- Accuracy-Adaptive Simulation of Transaction Level Models (MR, RSK), pp. 788–791.
- DATE-v2-2004-VorgRR #cost analysis #metric
- Measurement of IP Qualification Costs and Benefits (AV, MR, WR), pp. 996–1001.
- DATE-1999-RadetzkiSPN #analysis #data type #hardware #modelling #object-oriented #synthesis
- Data Type Analysis for Hardware Synthesis from Object-Oriented Models (MR, AS, WPR, WN), p. 491–?.
- DATE-1998-Putzke-RomingRN #flexibility #message passing
- A Flexible Message Passing Mechanism for Objective VHDL (WPR, MR, WN), pp. 242–249.