BibSLEIGH corpus
BibSLEIGH tags
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
3 × France
3 × Germany
Collaborated with:
R.S.Khaligh G.Schley W.Putzke-Röming W.Nebel N.Batzolis A.Vörg W.Rosenstiel A.Stammermann M.A.Kochte C.G.Zoellin M.E.Imhof H.Wunderlich S.D.Carlo P.Prinetto
Talks about:
model (4) transact (2) accuraci (2) network (2) object (2) simul (2) level (2) fault (2) adapt (2) chip (2)

Person: Martin Radetzki

DBLP DBLP: Radetzki:Martin

Contributed to:

PDP 20152015
PDP 20132013
DATE 20102010
DATE 20092009
DATE 20082008
DATE v2 20042004
DATE 19991999
DATE 19981998

Wrote 8 papers:

PDP-2015-SchleyR #fault tolerance
Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip (GS, MR), pp. 379–386.
PDP-2013-SchleyBR #fault #protocol
Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip (GS, NB, MR), pp. 454–461.
DATE-2010-KhalighR #adaptation #kernel #modelling #parallel #simulation
Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs (RSK, MR), pp. 1183–1188.
DATE-2009-KochteZIKRWCP #modelling #transaction #using #validation
Test exploration and validation using transaction level models (MAK, CGZ, MEI, RSK, MR, HJW, SDC, PP), pp. 1250–1253.
DATE-2008-RadetzkiK #adaptation #modelling #simulation #transaction
Accuracy-Adaptive Simulation of Transaction Level Models (MR, RSK), pp. 788–791.
DATE-v2-2004-VorgRR #cost analysis #metric
Measurement of IP Qualification Costs and Benefits (AV, MR, WR), pp. 996–1001.
DATE-1999-RadetzkiSPN #analysis #data type #hardware #modelling #object-oriented #synthesis
Data Type Analysis for Hardware Synthesis from Object-Oriented Models (MR, AS, WPR, WN), p. 491–?.
DATE-1998-Putzke-RomingRN #flexibility #message passing
A Flexible Message Passing Mechanism for Objective VHDL (WPR, MR, WN), pp. 242–249.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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