BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Belgium
1 × Portugal
1 × Sweden
3 × Germany
3 × USA
4 × France
Collaborated with:
G.Schumacher G.Jochens L.Kruse F.Oppenheimer J.Gerlach E.Schmidt M.Radetzki W.Putzke-Röming A.Korotaeva K.Schröder E.Moser L.Kabous A.Stammermann D.Zhang J.Oetjens R.Görgen J.B.Freuer G.Jerke D.Rabe A.Schallenberg A.Herrholz P.A.Hartmann K.Grüttner F.Colas-Bigey A.Fouilliart S.Häusler F.Poppen K.Hausmann A.Hahn T.Schubert J.Hanisch J.Appell F.Theeuwen G.Kamhi S.Miller S.B.Mentor Y.C.Wong J.Karmann E.Macii S.V.Kosonocky S.Curtis J.M.Rabaey D.Sylvester D.Blaauw K.Bernstein J.Frenkil M.Horowitz T.Sakurai A.Yang
Talks about:
model (10) system (8) power (6) design (4) synthesi (3) hardwar (3) object (3) flow (3) data (3) base (3)

Person: Wolfgang Nebel

DBLP DBLP: Nebel:Wolfgang

Facilitated 2 volumes:

DATE 2015Ed
DATE 2001Ed

Contributed to:

PDP 20152015
SAC 20132013
DATE 20092009
DATE 20082008
DAC 20072007
DATE DF 20042004
DAC 20032003
Ada-Europe 20012001
DATE 20012001
DATE 20002000
DATE 19991999
UML 19991999
Ada-Europe 19981998
DATE 19981998

Wrote 21 papers:

PDP-2015-KorotaevaN #embedded #manycore
Impact of Data Sharing on Co-Running Embedded Applications in Multi-core System (AK, WN), pp. 716–720.
SAC-2013-SchroderN #behaviour #resource management
Inter cloud capable dynamic resource management with model of behavior (KS, WN), pp. 408–410.
DATE-2009-OetjensGGN #automation #hardware #process
An automated flow for integrating hardware IP into the automotive systems engineering process (JHO, RG, JG, WN), pp. 1196–1201.
DATE-2009-SchallenbergNHHO #configuration management #framework #modelling #synthesis
OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems (AS, WN, AH, PAH, FO), pp. 970–975.
DATE-2008-FreuerJGN #constraints #design #higher-order #on the #verification
On the Verification of High-Order Constraint Compliance in IC Design (JBF, GJ, JG, WN), pp. 26–31.
DATE-2008-GruttnerONCF #modelling #refinement #synthesis
SystemC-based Modelling, Seamless Refinement, and Synthesis of a JPEG 2000 Decoder (KG, FO, WN, FCB, AMF), pp. 128–133.
DATE-2008-HauslerPHHN #analysis #design
Qalitative and Quantitative Analysis of IC Designs (SH, FP, KH, AH, WN), pp. 935–936.
DAC-2007-KamhiMMNWKMKC #design #power management #question #validation
Early Power-Aware Design & Validation: Myth or Reality? (GK, SM, SBM, WN, YCW, JK, EM, SVK, SC), pp. 210–211.
DATE-DF-2004-SchubertHGAN #design #evaluation
Evaluation of a Refinement-Driven SystemC™-Based Design Flow (TS, JH, JG, JEA, WN), pp. 262–267.
DAC-2003-RabaeySBBFHNSY
Reshaping EDA for power (JMR, DS, DB, KB, JF, MH, WN, TS, AY), p. 15.
AdaEurope-2001-OppenheimerZN #communication #interface #modelling
Modelling Communication Interfaces with COMIX (FO, DZ, WN), pp. 337–348.
DATE-2001-SchmidtJKTN #automation #memory management #modelling
Automatic nonlinear memory power modelling (ES, GJ, LK, FT, WN), p. 808.
DATE-2000-KruseSJSN #bound #constraints #data flow #graph #power management
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints (LK, ES, GJ, AS, WN), p. 737.
DATE-1999-JochensKSN #component #megamodelling
A New Parameterizable Power Macro-Model for Datapath Components (GJ, LK, ES, WN), p. 29–?.
DATE-1999-MoserN #case study #embedded
Case Study: System Model of Crane and Embedded Control (EM, WN), p. 721.
DATE-1999-RadetzkiSPN #analysis #data type #hardware #modelling #object-oriented #synthesis
Data Type Analysis for Hardware Synthesis from Object-Oriented Models (MR, AS, WPR, WN), p. 491–?.
UML-1999-KabousN #modelling #realtime #uml
Modeling Hard Real Time Systems with UML (LK, WN), pp. 339–355.
AdaEurope-1998-SchumacherN #ada #how #inheritance
How to Avoid the Inheritance Anomaly in Ada (GS, WN), pp. 53–64.
DATE-1998-Putzke-RomingRN #flexibility #message passing
A Flexible Message Passing Mechanism for Objective VHDL (WPR, MR, WN), pp. 242–249.
DATE-1998-RabeJKNO #performance #trade-off
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs (DR, GJ, LK, WN), pp. 356–361.
DATE-1998-SchumacherN #hardware #modelling #object-oriented #parallel
Object-Oriented Modelling of Parallel Hardware Systems (GS, WN), pp. 234–241.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.