Travelled to:4 × USA
Collaborated with:K.Sato C.Tanaka S.Murai T.Yahara K.Takahashi S.Nakamura K.Kinoshita H.Kanada T.Ogihara H.Fujiwara H.Tsuji K.Okazaki R.Katoh M.Tachibana
Talks about:system (5) design (4) masterslic (3) layout (3) reorgan (2) integr (2) comput (2) logic (2) array (2) part (2)
Person: Masayuki Terai
DBLP: Terai:Masayuki
Contributed to:
1990198219811978Wrote 5 papers:
- DAC-1990-TeraiTS #algorithm #assurance #constraints #design #layout
- A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint (MT, KT, KS), pp. 96–102.
- DAC-1982-TeraiKSY #layout
- A consideration of the number of horizontal grids used in the routing of a masterslice layout (MT, HK, KS, TY), pp. 121–128.
- DAC-1981-TanakaMNOTK #array #design #logic
- An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.
- DAC-1981-TanakaMTYOTKT #array #design #layout
- An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 (CT, SM, HT, TY, KO, MT, RK, MT), pp. 812–819.
- DAC-1978-NakamuraMTTFK #logic #named
- LORES — Logic Reorganization System (SN, SM, CT, MT, HF, KK), pp. 250–260.