Travelled to:4 × USA
Collaborated with:S.Murai K.Kinoshita H.Toyoshima S.Saruyama K.Muroi G.Yonemori Y.Takamatsu H.Fujiwara C.Tanaka S.Nakamura M.Terai
Talks about:system (5) generat (3) circuit (3) design (3) test (3) scan (3) gate (2) masterslic (1) synchron (1) parametr (1)
Person: Takuji Ogihara
DBLP: Ogihara:Takuji
Contributed to:
19891987198519831981Wrote 5 papers:
- DAC-1989-OgiharaMYM #effectiveness #generative #named #reliability #testing
- MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits (TO, KM, GY, SM), pp. 519–524.
- DAC-1987-OgiharaTM #design #named
- ASTA: LSI Design Management System (TO, HT, SM), pp. 530–536.
- DAC-1985-OgiharaSM #automation #generative #named #parametricity #testing
- PATEGE: an automatic DC parametric test generation system for series gated ECL circuits (TO, SS, SM), pp. 212–218.
- DAC-1983-OgiharaMTKF #bidirectional #design #generative #testing
- Test generation for scan design circuits with tri-state modules and bidirectional terminals (TO, SM, YT, KK, HF), pp. 71–78.
- DAC-1981-TanakaMNOTK #array #design #logic
- An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.