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Travelled to:
1 × Italy
4 × France
4 × Germany
Collaborated with:
M.S.Reorda M.Rebaudengo S.Campagna F.Corno L.Sterpone P.Bernardi O.Goloubeva F.Abate F.L.Kastensmidt C.Meinhardt R.Reis G.Squillero M.Torchiano P.Prinetto M.Lajolo L.Lavagno M.Martina G.Masera A.Molino F.Vacca P.Cheynet B.Nicolescu R.Velazco M.Bellato D.Bortolato A.Candelori M.Ceschia A.Paccagnella P.Zambolin
Talks about:
microprocessor (3) system (3) effect (3) evalu (3) experiment (2) processor (2) programm (2) configur (2) approach (2) generat (2)

Person: Massimo Violante

DBLP DBLP: Violante:Massimo

Contributed to:

DATE 20122012
DATE 20092009
DATE Designers’ Forum 20062006
DATE v1 20042004
DATE 20032003
DATE 20012001
SCAM 20012001
DATE 20002000
DATE 19981998

Wrote 13 papers:

DATE-2012-CampagnaV #architecture #detection #fault #hybrid #validation
An hybrid architecture to detect transient faults in microprocessors: An experimental validation (SC, MV), pp. 1433–1438.
DATE-2009-AbateSVK #case study #functional
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs (FA, LS, MV, FLK), pp. 1226–1229.
DATE-2009-ReordaVMR #embedded #low cost
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips (MSR, MV, CM, RR), pp. 352–357.
DATE-DF-2006-MartinaMMVSV #approach #programmable
A new approach to compress the configuration information of programmable devices (MM, GM, AM, FV, LS, MV), pp. 48–51.
DATE-v1-2004-BellatoBBCCPRRVZ #memory management
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA (MB, PB, DB, AC, MC, AP, MR, MSR, MV, PZ), pp. 584–589.
DATE-v1-2004-GoloubevaRV #automation #generative #validation
Automatic Generation of Validation Stimuli for Application-Specific Processors (OG, MSR, MV), pp. 188–193.
DATE-2003-BernardiRRV #approach #embedded #programmable
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories (PB, MR, MSR, MV), pp. 10720–10725.
DATE-2003-RebaudengoRV #analysis #fault #pipes and filters
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor (MR, MSR, MV), pp. 10602–10607.
DATE-2001-CheynetNVRRV #automation #evaluation #program transformation #safety
System safety through automatic high-level code transformations: an experimental evaluation (PC, BN, RV, MR, MSR, MV), pp. 297–301.
DATE-2001-CornoRSV #on the
On the test of microprocessor IP cores (FC, MSR, GS, MV), pp. 209–213.
SCAM-2001-RebaudengoRVT #compilation #generative #text-to-text
A Source-to-Source Compiler for Generating Dependable Software (MR, MSR, MV, MT), pp. 35–44.
DATE-2000-LajoloRRVL #co-evolution #dependence #design #framework
Evaluating System Dependability in a Co-Design Framework (ML, MR, MSR, MV, LL), pp. 586–590.
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection (FC, PP, MSR, MV), pp. 670–677.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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