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Travelled to:
4 × France
5 × Germany
Collaborated with:
M.S.Reorda E.Sánchez O.Ballan M.Rebaudengo M.Violante M.Grosso G.Masera F.Quaglio M.Bonazza M.Schillaci G.Squillero A.Riefert L.M.Ciganda M.Sauer B.Becker A.Touati A.Bosio L.Dilillo P.Girard A.Virazel M.Bellato D.Bortolato A.Candelori M.Ceschia A.Paccagnella P.Zambolin
Talks about:
test (7) base (4) processor (3) function (3) approach (3) effect (3) fault (3) softwar (2) memori (2) embed (2)

Person: Paolo Bernardi

DBLP DBLP: Bernardi:Paolo

Contributed to:

DATE 20152015
DATE 20142014
DATE 20132013
DATE 20112011
DATE 20082008
DATE 20062006
DATE 20052004
DATE v1 20042004
DATE 20032003

Wrote 9 papers:

DATE-2015-TouatiBDGVBR #functional #power management #source code #testing
Exploring the impact of functional test programs re-used for power-aware testing (AT, AB, LD, PG, AV, PB, MSR), pp. 1277–1280.
DATE-2014-RiefertCSBRB #approach #automation #effectiveness #fault #functional #generative #testing
An effective approach to automatic functional processor test generation for small-delay faults (AR, LMC, MS, PB, MSR, BB), pp. 1–6.
DATE-2013-BernardiBSRB #embedded #fault #identification #online
On-line functionally untestable fault identification in embedded processor cores (PB, MB, ES, MSR, OB), pp. 1462–1467.
DATE-2011-BernardiGSB #fault #self #testing
Fault grading of software-based self-test procedures for dependable automotive applications (PB, MG, ES, OB), pp. 513–514.
DATE-2008-BernardiR #novel #testing
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers (PB, MSR), pp. 194–199.
DATE-2006-BernardiSSSR #cost analysis #effectiveness
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs (PB, ES, MS, GS, MSR), pp. 412–417.
DATE-2005-BernardiMQR04 #approach #logic #testing #using
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study (PB, GM, FQ, MSR), pp. 228–233.
DATE-v1-2004-BellatoBBCCPRRVZ #memory management
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA (MB, PB, DB, AC, MC, AP, MR, MSR, MV, PZ), pp. 584–589.
DATE-2003-BernardiRRV #approach #embedded #programmable
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories (PB, MR, MSR, MV), pp. 10720–10725.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.