Travelled to:2 × France
3 × USA
Collaborated with:D.Blaauw V.Zolotov R.Panda I.N.Hajj C.Oh S.Raja F.Varadi J.Geada R.Gandikota K.Chopra D.Sylvester A.Glebov S.Gavrilov I.Algor
Talks about:nois (6) analysi (4) crosstalk (2) model (2) gate (2) interconnect (1) transistor (1) aggressor (1) techniqu (1) complet (1)
Person: Murat R. Becer
DBLP: Becer:Murat_R=
Contributed to:
20082007
200420032002Wrote 5 papers:
- DAC-2008-RajaVBG #analysis #modelling #performance
- Transistor level gate modeling for accurate and fast timing, noise, and power analysis (SR, FV, MRB, JG), pp. 456–461.
- DAC-2007-GandikotaCBSB #analysis #set
- Top-k Aggressors Sets in Delay Noise Analysis (RG, KC, DB, DS, MRB), pp. 174–179.
- DATE-v2-2004-GlebovGZOPB #analysis
- False-Noise Analysis for Domino Circuits (AG, SG, VZ, CO, RP, MRB), pp. 784–789.
- DAC-2003-BecerBAPOZH #reduction
- Post-route gate sizing for crosstalk noise reduction (MRB, DB, IA, RP, CO, VZ, INH), pp. 954–957.
- DATE-2002-BecerZBPH #analysis #using
- Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model (MRB, VZ, DB, RP, INH), pp. 456–463.