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Used together with:
nois (17)
analysi (9)
delay (6)
model (6)
interconnect (6)

Stem crosstalk$ (all stems)

50 papers:

DATEDATE-2015-DuongNXWTBYWW #analysis
Coherent crosstalk noise analyses in ring-based optical interconnects (LHKD, MN, JX, ZW, YT, SLB, PY, XW, ZW), pp. 501–506.
DATEDATE-2013-KumarK #3d
Crosstalk avoidance codes for 3D VLSI (RK, SPK), pp. 1673–1678.
CASECASE-2012-ChoiKKKHP #development #fault
Development of joint torque sensor applied to compensate crosstalk error (SyC, TKK, DYK, BSK, JHH, CWP), pp. 1086–1088.
DACDAC-2010-XieNXZLWYWL #analysis #fault
Crosstalk noise and bit error rate analysis for optical network-on-chip (YX, MN, JX, WZ, QL, XW, YY, XW, WL), pp. 657–660.
DATEDATE-2010-PengYTC #fault #process
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk (KP, MY, MT, KC), pp. 1426–1431.
DACDAC-2008-DuanZK #design
Forbidden transition free crosstalk avoidance CODEC design (CD, CZ, SPK), pp. 986–991.
DACDAC-2008-GandikotaBS #analysis #modelling #statistics
Modeling crosstalk in statistical static timing analysis (RG, DB, DS), pp. 974–979.
DATEDATE-2008-HalakY #optimisation
Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods (BH, AY), pp. 438–443.
DATEDATE-2007-GaneshpureK #automation #fault #generative #interactive #multi
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults (KPG, SK), pp. 540–545.
DATEDATE-2006-LiuH #logic #synthesis
Crosstalk-aware domino logic synthesis (YYL, TH), pp. 1312–1317.
DATEDATE-2006-OmanaCRM #detection #fault #low cost #reliability
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects (MO, JMC, DR, CM), pp. 170–175.
DATEDATE-2006-RosselloS #fault #identification
A compact model to identify delay faults due to crosstalk (JLR, JS), pp. 902–906.
DATEDATE-DF-2006-NazarianPGB #named #set #statistics
STAX: statistical crosstalk target set compaction (SN, MP, SKG, MAB), pp. 172–177.
DACDAC-2004-DeogunRSB #encoding #reduction
Leakage-and crosstalk-aware bus encoding for total power reduction (HD, RRR, DS, DB), pp. 779–782.
A Crosstalk Aware Interconnect with Variable Cycle Transmission (LL, NV, MTK, MJI), pp. 102–107.
Exploiting Crosstalk to Speed up On-Chip Buse (CD, SPK), pp. 778–783.
DATEDATE-v2-2004-GuptaK #performance #statistics
A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk (SG, SK), pp. 1110–1115.
DATEDATE-v2-2004-LampropoulosAR #using
Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique (ML, BMAH, PMR), pp. 1372–1373.
DATEDATE-v2-2004-LiuWH #logic #synthesis
Crosstalk Minimization in Logic Synthesis for PLA (YYL, KHW, TH), pp. 790–795.
DATEDATE-v2-2004-RanKWM #analysis
Eliminating False Positives in Crosstalk Noise Analysis (YR, AK, YW, MMS), pp. 1192–1197.
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk (JLR, JS), pp. 954–961.
DACDAC-2003-BecerBAPOZH #reduction
Post-route gate sizing for crosstalk noise reduction (MRB, DB, IA, RP, CO, VZ, INH), pp. 954–957.
DACDAC-2003-ChaiKRTWM #analysis
Temporofunctional crosstalk noise analysis (DC, AK, YR, KHT, YW, MMS), pp. 860–863.
Crosstalk noise in FPGAs (YR, MMS), pp. 944–949.
DACDAC-2003-RenG #performance
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses (JR, MRG), pp. 592–597.
DATEDATE-2003-ChoiR #logic
A New Crosstalk Noise Model for DOMINO Logic Circuits (SHC, KR), pp. 11112–11113.
DATEDATE-2003-SmeySM #reduction
Crosstalk Reduction in Area Routing (RMS, BS, PHM), pp. 10862–10867.
DATEDATE-2003-Zhou #verification
Timing Verification with Crosstalk for Transparently Latched Circuits (HZ), pp. 10056–10061.
DACDAC-2002-KrauterW #analysis
Variable frequency crosstalk noise analysis: : a methodology to guarantee functionality from dc to fmax (BK, DW), pp. 665–668.
DACDAC-2002-MaH #constraints #towards
Towards global routing with RLC crosstalk constraints (JDZM, LH), pp. 669–672.
DACDAC-2002-MortonD #estimation
Crosstalk noise estimation for noise management (PBM, WWMD), pp. 659–664.
DATEDATE-2002-BecerZBPH #analysis #using
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model (MRB, VZ, DB, RP, INH), pp. 456–463.
DATEDATE-2002-ChenM #design #metric #physics
Closed-Form Crosstalk Noise Metrics for Physical Design Applications (LHC, MMS), pp. 812–819.
DATEDATE-2002-MacchiaruloMP #energy
Wire Placement for Crosstalk Energy Minimization in Address Buses (LM, EM, MP), pp. 158–162.
Crosstalk Alleviation for Dynamic PLAs (TKT, TKT, SCC), pp. 683–687.
DACDAC-2001-ChenBD #embedded #fault #testing #using
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores (LC, XB, SD), pp. 317–320.
DACDAC-2001-XiaoM #analysis #correlation #functional #identification
Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification (TX, MMS), pp. 653–656.
DACDAC-2001-ZhouSN #analysis #fixpoint
Timing Analysis with Crosstalk as Fixpoints on Complete Lattice (HZ, NVS, WN), pp. 714–719.
DATEDATE-2001-Bazargan-SabetI #modelling #tool support #verification
Modeling crosstalk noise for deep submicron verification tools (PBS, FI), pp. 530–534.
DATEDATE-2001-FavalliM #detection #fault #optimisation
Optimization of error detecting codes for the detection of crosstalk originated errors (MF, CM), pp. 290–296.
Crosstalk noise in future digital CMOS circuits (CW, RG, AW, UR), pp. 331–335.
DACDAC-2000-BaiDR #self
Self-test methodology for at-speed test of crosstalk in chip interconnects (XB, SD, JR), pp. 619–624.
DACDAC-2000-KimNK #logic #synthesis
Domino logic synthesis minimizing crosstalk (KWK, UN, SMK), pp. 280–285.
DATEDATE-2000-HiroseY #reduction
A Bus Delay Reduction Technique Considering Crosstalk (KH, HY), pp. 441–445.
DATEDATE-2000-RingeLB #analysis
Static Timing Analysis Taking Crosstalk into Account (MR, TL, EB), pp. 451–455.
DATEDATE-2000-SuCHCL #metric
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses (CS, YTC, MJH, GNC, CLL), pp. 527–531.
DACDAC-1999-SaxenaL #using
Crosstalk Minimization Using Wire Perturbations (PS, CLL), pp. 100–103.
Timing and Crosstalk Driven Area Routing (HPT, LS, CS), pp. 378–381.
DACDAC-1998-ZhouW #constraints
Global Routing with Crosstalk Constraints (HZ, DFW), pp. 374–377.
DATEDATE-1998-WangK #reduction
A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction (DW, ESK), pp. 466–470.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.