Travelled to:3 × USA
Collaborated with:F.N.Najm K.R.Heloue G.Nabaa M.M.Khellah V.De
Talks about:variat (2) leakag (2) reduc (2) architectur (1) ternari (1) process (1) current (1) compens (1) within (1) voltag (1)
Person: Navid Azizi
DBLP: Azizi:Navid
Contributed to:
200720062005Wrote 4 papers:
- DAC-2007-HeloueAN #correlation #estimation #modelling
- Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation (KRH, NA, FNN), pp. 93–98.
- DAC-2006-AziziN #product line
- A family of cells to reduce the soft-error-rate in ternary-CAM (NA, FNN), pp. 779–784.
- DAC-2006-NabaaAN #adaptation #architecture #process
- An adaptive FPGA architecture with process variation compensation and reduced leakage (GN, NA, FNN), pp. 624–629.
- DAC-2005-AziziKDN #design #power management #scalability
- Variations-aware low-power design with voltage scaling (NA, MMK, VD, FNN), pp. 529–534.